Logical Equivalence Checking Netlist vs Netlist problem.

[raghavathej]

Hi,

I am comparing Plain synthesis Netlist vs Low power synthesis Netlist( i have only used clock gating low power technique). I am using Cadence Tools. i find that there are unmapped points in Low power netlist ( Red coloured "U") which is of clock gating as shown in the attachment. Should i ignore those?...Since clock gating is not present in plain synthesis netlist. i have enable flatten model -clock gating.

 

[vijay12884]

Hi,

I am comparing Plain synthesis Netlist vs Low power synthesis Netlist( i have only used clock gating low power technique). I am using Cadence Tools. i find that there are unmapped points in Low power netlist ( Red coloured "U") which is of clock gating as shown in the attachment. Should i ignore those?...Since clock gating is not present in plain synthesis netlist. i have enable flatten model -clock gating.

NO! You should not ignore these. What you need to do is. As per what you have written it seem you "Plain SYnthesis Netlist" Is "Golden" and your "Low Power Synthesis NEtlist" is "Revised" . Also as you have written that you can see the unmapped points at cgc cells. The what you need to do is? add the cgc libs cells "Verilog definition" of the cells, at the golden side- from where you are reading all the files and parsing the same. so as to tell the tool to look for these cells and map them.

Cheers