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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dco1 is
Port ( IDC : in STD_LOGIC;
C : in STD_LOGIC;
B : in STD_LOGIC;
IDOUT : out STD_LOGIC);
end dco1;
architecture Behavioral of dco1 is
component tff is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
QT : out STD_LOGIC);
end component;
signal RT : std_logic := '0';
signal Tout : std_logic := '0';
signal temp_1 :std_logic;
signal temp_2 :std_logic;
signal a1 :std_logic := '0';
signal b1 :std_logic :='0';
signal c1 :std_logic:='0';
begin
t0: Tff port map (CLK=>IDC, RESET=>RT,QT=>temp_1);
process (IDC, C, B)
begin
if (rising_edge(IDC)) then
a1 <= '1';
elsif(falling_edge(IDC)) then
a1 <='0';
end if;
if (rising_edge(C)) then
b1 <= '1';
elsif(falling_edge(C)) then
b1 <='0';
end if;
if (rising_edge(B)) then
c1 <= '1';
elsif(falling_edge(C)) then
c1 <='0';
end if;
--temp_2 <= Tout and temp_1;
--IDOUT <= (not IDC) and (not temp_2);
end process;
end Behavioral;