Logic synthesis just translate RTL to netlist , and some physcial information is not accurate (such as wire load model, cell place).
phsysical synthesis can get some physcial information from layout, it physcial information is accurate than logic synthesis. And some physcial synthesis not only translate RTL to netlist , it can translate RTL to Layout.
And usally some logic synthesis tools have the command to read some physical information. such as "read_spef" in dc to read floorplan . But how to use it , i don't clearly.