Logic synthesis, duty cycle of clock

[engr]

Hi All

Does the duty cycle of clock matter , when defining the clock.

what happens if i define clock "50 percent" and "non 50 percent duty cycle", am i free to define duty cycle of the clock.
Thanks in adavnec

 

[rjainv]

You are not free to define duty cycle of the clock. It will come from the specification of source that is generating the clock, it could be a PLL or a crystal through a divider or directly.

It would matter if you have both posedge as well as negedge triggered flops or latches in design.

 

[dcreddy1980]

If you are talking about synthesis, You can define the duty cycle of the clock and analyize the limitations of your design and this can be done with :

create_clock command has the option to define your duty cycle -->
create_clock –period 4 –waveform {0 3} [get_ports {clk}]

Here i have done it for 75% clk high and 25% clk low