logic rise time and fall time

[lewisP]

A logic buffer's input rise time and fall time is different compared to a buffers output rise time and fall time, why is that?

Each TTL and CMOS families have different rise times and fall times which requires a clock signal to adjusts its pulse width for the logic family. why does a clocks pulse width need to be adjusted when using different logic families to adjust to the rise times and fall times?

the loading circuit can change a logic signals rise time and fall time. What else can change a logic signals rise time and fall time from input to output?

 

[KlausST]

Hi,

the output rise time depends on logic family, VCC, and load impedance.

The input rise time specified as a minimum dU/dt. This is because some logic families are not stable when the input signal inbetween true LOW (often 0.7V) and true HIGH (often 2.0V). It may draw increased VCC current and it may oscillate. Therefore the input signal needs to travel fast enough between low and high level to prevent from oscillation.


Klaus