Hi,
I have a basic doubt regarding the timing calculation for a multiplexer with an enable input. The mux is a part of the combinational logic path between a set of input and output registers.
I need to find the maximum logic delay in this path in order to compute the max clock frequency, as well as any hold time violations.
How are the mux 'delay from data' or 'delay from enable' to be used for finding the logic path delay?
In fact, the most accurate of the equations that represent the maximum amount of time allowed for your logic circuit to compute the outputs is given by:
If your enable pin will hold constant at operation time .
you can set case analysis 1 enable_pin the do STA , and then set case analysis 0 and do STA again . TA tool will decided the longest path .
If not , just do STA .