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Logic for getting only two digits out of a binary number

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vinodkumar

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Hi friends ,my doubt is ,If i gave input has ex:1529 in binary form ,if i want only 29,i,e, last two digits with out converting to BCD seperated,wht could be the logic with minimum HW.
 

ameed

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Re: basic doubt

hi vinod,

if you want code releted to your design ,
go through opencores.com:idea:


thanx......
 

echo47

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basic doubt

If your device has spare block RAMs available, try using a lookup table.

The two least-significant bits can bypass the table.
 

vinodkumar

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Re: basic doubt

HI echo,
iam sorry iam new to FPGA,i dont know much of the stuff tht how to USE BRAM,LUT ets,my purpose was to do 1529 mod 100,2350 mod 100,like this.input is integer,for these i will get 29,50 etc as output right,so as modulo operator not synth,i thought of going for this.
 

echo47

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basic doubt

Maybe this Verilog example will help you. It inputs values from 0 to 8191, and outputs the modulo 100 value.
When using Xilinx ISE 9.1.03i and Spartan-3, it consumes only one block RAM, and no other logic.
Code:
module top (clk, idata, odata);
  input             clk;
  input      [12:0] idata;
  reg         [4:0] rom [0:2047];
  output reg  [6:0] odata;

  integer n;
  initial
    for (n=0; n<2048; n=n+1)
      rom[n] = n % 25;

  always @ (posedge clk) begin
    odata[6:2] <= rom[idata[12:2]];
    odata[1:0] <= idata[1:0];
  end
endmodule
Most HDL synthesis tools don't fully support the modulo operator because it usually requires a messy division.
Xilinx XST accepts it in the "initial" section.
 

    vinodkumar

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avimit

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Re: basic doubt

Hi,
The mod operator is not synthesizeable unless its a mod (2^n). Well that is true.
One way then to find mod is by repetitive addition and comparison, and that will consume a lot of area, and will affect timing as well, unless you have a few clock cycles to implement it.
Kr,
Avi
http://www.vlsiip.com
 

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