Logic Design -> Interview Questions

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Hi All,

Thank you!

Warpspeed

If you really want to make some nervous young applicant really sweat, ask about metastability.

ivlsi

I know about metastability and many other things...

Like this one: "There is a stream of bits. Suppose LSB comes first. Implement FSM, which detect when the incoming binary number is modulo-5. The stream is infinite."

Super Moderator
Staff member
I know about metastability and many other things...

Like this one: "There is a stream of bits. Suppose LSB comes first. Implement FSM, which detect when the incoming binary number is modulo-5. The stream is infinite."

How is that a "tricky" question...it's just a design question.

I think tricky questions are more like open ended questions where the interviewee has to ask questions to clarify the question into something that can be answered. e.g. What is the net effect of a metastable event on the functionality of a system.

Now the interviewee is sweating wondering what is meant by the net effect on system functionality. Either the interviewee rambles on not answering anything or if they're savvy they ask some questions about what is meant by a functional failure and what is meant by net effects (i.e. they ask if we mean transition delay, missed transition, etc)

This kind of question is is typically used by some to check how someone thinks under pressure when they have a lack of information. Do they investigate or just try to act like they know something and spew nonsense. :wink:

ivlsi

Ok, I meant "not trivial complicated Logic Design questions, which might be asked on the interviews"

Sarathkumarkj

Newbie level 2
1. Verilog HDL originated at
A. AT&T Bell Laboratories
B. Defence Advanced Research Projects Agency (DARPA)
C. Gateway Design Automation
D. Institute of Electrical and Electronics Engineers (IEEE)
2. Verilog is an IEEE standard
A. IEEE 1346
B. IEEE 1364
C. IEEE 1394
D. IEEE 1349
3. Which level of abstraction level is available in Verilog but not in VHDL?
A. Behavioral level
B. Dataflow level
C. Gate level
D. Switch level
4. In verilog h1234 is a
D. It is invalid notation
5. Which logic level is not supported by verilog?
A. U
B. X
C. Z
D. None of the above
6. If a net has no driver, it gets the value
A. 0
B. X
C. Z
D. U
7. Default value of reg is
A. 0
B. X
C. Z
D. U
8. The task $stop is provided to A. End simulation B. Suspend simulation C. Exit simulator D. None of the above 9. Externally, a output port must always connected to a A. net only B. a reg only C. either net or reg D. None of the above 10. If A= 4b011 and B= 4b0011, then the result of A**B will be A. 6 B. 9 C. 27 D. Invalid expression 11. If A= 4b001x and B= 4b1011, then result of A+B will be A. 110x B. 1100 C. xxxx D. None of the above 12. If A= 41xxz and B= 4b1xxx, then A= = =B will return A. 1 B. X C. Z D. 0 13. Result of 9% -2 will be A. 4 B. 4.5 C. -1 D. +1 14. Initial value of a=1 and b=2, then what will be final value if always @ (posedge clock) a=b; always @ (posedge clock) b=a; A. a= 2, b=1 B. a= 1, b=2 C. Both a and b will have same value either 0 or 1 D. None of the above 15. Initial value of a=1 and b=2, then what will be final value if always @ (posedge clock) a<=b; always @ (posedge clock) b<=a; A. a= 2, b=1 B. a= 1, b=2 C. Both a and b will have same value either 0 or 1 D. None of the above 16. Given the following Verilog code, what value of "a" is displayed? always @ (clock) begin a = 0; a <= 1;$display(a);
end
A. 0
B. 1
C. either 0 or 1 depending on depending on simulator implementation
D. None of the above
17. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list?
A. No
B. Yes
C. It depends on the coding style
D. None of these
18. How many flops will be synthesized by the given code?
always @ (posedge clock) begin
Q1<=d;
Q2<=q1;
Q3<=q2;
end
A. 1
B. 2
C. 3
D. None of the above
19. Which is not a correct method of specifying time scale in verilog?
A. 1ns/1ps
B. 10ns/1ps
C. 100ns/100ps
D. 100ns/110ps
20. If time scale is defined as timescale 10ns/1ns and #1.55 a = b; then 'a' gets 'b' after
A. 10ns
B. 11 ns
C. 15.5ns
D. 16ns
21. A task can have arguments of type
A. Input only
B. Output only
C. Both input and output
D. All input, output and inout

22. If a recursive function is called concurrently from two locations, then
A. Recursive function can have multiple calls concurrently
B. It will result give ambiguous results
C. It will result in an error
D. Simulation will hang up
23. Which operators has highest precedence in verilog
A. Unary
B. Multiplication
D. Conditional
24. In the given code snippet, statement 2 will executed at
initial
begin
#5 x= 1’b0; // statement 1
# 15 y= 1b’1; //statement 2
End
A. 15
B. 20
C. 5
D. Current simulation time
25. Variable and signal which will be updated first?
A. Variable
B. Signal
C. Can’t say
D. None of the above

dave_59

Sarathkumarkj, you need to update your quiz to the 21st century. There is no longer an IEEE Verilog standard. it has been replaced by IEEE 1800 in 2009, the current revision is 1800-2012

Super Moderator
Staff member
Sarathkumarkj, your post also does not address the OP's question, which isn't about generic questions that you give to someone fresh out of school.

Ok, I meant "not trivial complicated Logic Design questions, which might be asked on the interviews"
Basically this says I want a good design question that has to be solved to prove the interviewee can actually design something and not just talk a good show.

Questions like:

"show me how you would architect a 128-tap 256 channel fir filter that will run at 300 MHz in a Kintex7"
"design a LDPC encoder"
"design an MPEG4 encoder and decoder"
"design our next product for us, make sure you finish by the end of your interview, if you want the job"
;-)

FYI, I'm exaggerating a little bit, but I'm sure you get the picture.

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