Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Well it matters!
Typically lock is detected by sensing the pulse width of the up and down signals and if they are too narrow than a set limit for a sufficiently long time phase lock is declared. For a fractional-N pll, due to the contant phase deviations, this window has to be larger than that set for an integer pll.
hmsheng, You could OR the UP and DN signals and use that signal to select a discharge path for a capacitor that is being fed by a constant current that is a ratio of the discharge current. I hope you get the idea at the first level.
Or digitally detect whether the signal is shorter than the propagation delays of a few gates for both UP and DN and declare the lock.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
