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loading FPGA from ROM

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Member level 2
Mar 2, 2007
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fpga rom jtag

can anyone explain me ,how FPGA is loaded from ROM automatically at power up?
explan the logic behind?

loading fpga

Hi Praveen,
The FPGA enters into JTAG mode, this is taken care by on chip power PC. Once the JTAG is enabled the FPGA is configured based on information present in ROM or FLASH. Once the FPGA is configured then JTAG is disabled and the FPGA enters into normal operation

If you any doubt u can ask
Thanks and Regards

how to fpga connect rom

hi satya
so there is powerPC ,which enable the jtag to load FPGA.where POWERPC located.on chip means?

rom fpga

Hi Praveen,
In FPGA the powerPC is present, it may be external in some old version FPGA usually it comes with flash

hi satya,
so powerPc is inbuilt into all FPGA,wat are the other works of powerPC inside FPGA?whether powerPC is put as a core?

PowerPC will come as periperal to FPGA(means outside FPGA)?is it interfaced while board design?

The attached file is the connection of prom with fpga and the fpga acces with prom. check out it is useful

Hi praveen,
The document sent by rajsrikanth explains clearly about how a configuration is loaded to FPGA and the related logic.
There is no point in keeping the powerPC out side FPGA, its main function is configuring FPGA. If we take PROM its size is big and desipates considerable amount of power during runtime. So, its waste to keep inside the FPGA. But in recent version of FPGA the PROM is inbuilt, this is posible after reducing some drawbacks.
The attachment is removed.
Can anybody pl upload it again


here is the attachment..

Added after 2 minutes:

whether looking for some other attachments...kidly reply with details

xapp482.pdf describes a special situation - downloading program code from PROM into the CPU inside the FPGA. However, most FPGAs don't have any embedded CPU (such as PowerPC), and most FPGA projects don't use any soft CPU core (such as MicroBlaze).

Most FPGAs download their configuration serially from a special flash PROM that's designed to talk to the particular type of FPGA. (The PROM-to-FPGA connection is not JTAG.) Some FPGAs can download their configuration from an ordinary parallel PROM using regular address and data lines. Here are some Xilinx configuration PROMs:


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