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The FPGA enters into JTAG mode, this is taken care by on chip power PC. Once the JTAG is enabled the FPGA is configured based on information present in ROM or FLASH. Once the FPGA is configured then JTAG is disabled and the FPGA enters into normal operation
If you any doubt u can ask
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The document sent by rajsrikanth explains clearly about how a configuration is loaded to FPGA and the related logic.
There is no point in keeping the powerPC out side FPGA, its main function is configuring FPGA. If we take PROM its size is big and desipates considerable amount of power during runtime. So, its waste to keep inside the FPGA. But in recent version of FPGA the PROM is inbuilt, this is posible after reducing some drawbacks.
xapp482.pdf describes a special situation - downloading program code from PROM into the CPU inside the FPGA. However, most FPGAs don't have any embedded CPU (such as PowerPC), and most FPGA projects don't use any soft CPU core (such as MicroBlaze).
Most FPGAs download their configuration serially from a special flash PROM that's designed to talk to the particular type of FPGA. (The PROM-to-FPGA connection is not JTAG.) Some FPGAs can download their configuration from an ordinary parallel PROM using regular address and data lines. Here are some Xilinx configuration PROMs: https://www.xilinx.com/products/silicon_solutions/proms/index.htm