At some point, every regulator's HF PSRR becomes a
function of the output filter and not the control loop.
This could be sub-100kHz for an old LM317, or over 1MHz
for some of the newer LDOs which offer improved HF
PSRR as a feature to make them useful as "cleanup"
for higher frequency switching power supplies.
In this case I recommend that first you assign the
risetime an application-realistic worst case; a 1uS
risetime on a large current step is not, usually. That
would prefer to have enough bulk filter to soak up
a lot of the current close-in, and give the control
loop the time it needs to catch up. What does the
load say to expect, or are you just making up test
challenges with characteristics the regulator just
can't be expected to meet?
You also need to consider that at Iload=0, the
control loop might be "wound up" trying to make
zero output current, and respond poorly to the load
step because it's not really closed loop linear. Might
instead do something like 1mA to 20mA, and see if
that behaves better.