EDIT...the attached works quite well, settling out after a while quite equally...but i forgot to connect up the top current equalisation error amp properly...so it works, but is wrongly connected up ....END OF EDIT
Yes, i think the integrator that deals with equalising the currents should be of a bandwidth some 10x lower than the actual regulation error amps....but the sim takes ages to run if you do like that.
The attached is doing it with linear regs in pllel, so the sim runs a bit quicker. There are two 50mV voltage sources that are needed to make it work (V10 and V16)....i think these are to make sure that the SMPS that first becomes "master"...then stays as "master. But im not so sure yet what these voltages do.
I think that it relys on one of them becoming "master", and then staying as master.....otherwise, if the master changes, then it becomes chaotic and vout suffers disturbances.
Such a voltage source exists in UC3902...and im guessing that this is its purpose...ie, to "secure the master as master"?
It seems a strange thing that the system doesnt know who is master till it starts up......but it must work out who's master very quickly, otherwise it cant work.
The sizing of the 50mV voltage source seems to depend on the current sense resistor max voltage and the volt drop to th eload along the circuit conductors......if too much current trace resistance is there, then the UC3902 method literally doesnt work it seems?....or it needs the 50mV volt source to be increased?
LTspice and jpeg as attached