little problem with gain in a ring oscilator

[morecode1234567890]

square gain

I am simulating a ring oscilator in typ conditions, when i change the librarys that make typ conditions, worst case, the gain of each stage y lower than 1 so I lose my signal. If the design is modified for work in that conditions, the gain in the circuit is very high, so the signal is not sin as i need it. Have you any idea.

Sorry for my english.
Thx in advance.

 

[flatulent]

filter

You need the oscillator to work under worst case conditions and so you have to do something about the ordinary conditions. You have three choices.

1. Filter the square wave before using it.

2. Have the circuit it drives not be hampered by a square wave. All sorts of mixers work well with square wave oscillator outputs.

3. Have some sort of variable gain circuit that measures the output and reduces the gain of one or more stages.

 

[morecode1234567890]

I know that i must introduce something that control the gain of the circuits, but, this make the system get bigger, much bigger than 4 differential pairs(1 inverter 3 non inverter). The filter is a nice IDEA, but, when i work in the worst case, the frecuency of the ring goes down, so, i do not know...
thx
bye.

 

[sutapanaki]

Control the gain as was said if you really need sin output. You said you have a diff stage, then you can adjust the gain by selecting the proper current. Shouldn't be very difficult and area consuming.
BTW if you need a sin output why did you chose to use ring oscillator?

 

[Pim]

I have once spent quite some time in designing a ringsocillator used in a PLL in 0.35 um CMOS. You must *always* see to that the ring gain is larger than one. Otherwise your design will be a disaster since it won't oscillate. Therefore you must simulate for the worst conditions regarding gain (which was process corner WS, max temperature for me).

Also, the frequency of the oscillator will very much be dependent on the process corner, temperature and component tolerances. The ringoscillator design idea is a nice one, but it produces much noise. Therefore you must see to that the output impedance of each stage is low, which brings about large capacitors, which consumes space on the chip.

To use a filter is also an idea to make the output signal more sinus-like, however, the breakpoint frequency of the lowpass filter must be about the same as the nominal output signal's frequency, which leads to that the output signal's amplitude after the lowpass filter will very much depend on the oscillator's frequency.

I managed to solve the main problems by using feedback/feedforward loops in the signal chain between the different stages (lowered the distortion), and amplitude compensation that was controlled by the frequency controlling signal. But it was very difficult to optimize the whole circuit regarding process corners, temperature, supply voltage variations, component tolerance (especially resistors). I used Cadence IC 4.4.3 for the simulations and sure I would have wished that I had Neolinear Neocircuit too (Neocircuit is a automatic optimization program, if anyone has it, please drop me a PM ).

I wish you good luck.

/Pim

I am simulating a ring oscilator in typ conditions, when i change the librarys that make typ conditions, worst case, the gain of each stage y lower than 1 so I lose my signal. If the design is modified for work in that conditions, the gain in the circuit is very high, so the signal is not sin as i need it. Have you any idea.

Sorry for my english.
Thx in advance.

 

[electronrancher]

Are you running your W/L too close to the edge of saturation in order to make the sinewave soft? Then your mosfets would probably fall out of oscillation with slow models (thick glass, low doping) and start becoming square with fast models (thin oxide, high doping)..

It's hard to get a sine wave out of an inverter unless you are pushing it into triode - even then you are right on the edge of too soft, or too hard..

Remember, inverters are snappy by nature, so they are actually no good for sine wave. The biggest problem will be hot carriers. Running an inverter at midpoint sinks a lot of current - these carriers speed up underneath the gate and break bonds, "etching" the surface under the gate, and making mosfets slow..


Can you use a triangle? Charging/discharging a 10pf cap can be a very fast oscillator, then it's easy to filter into a sine with OTA-style diff amp in an RC configuration. Search google for "sine wave lm13600". and "OTA" to get all the blocks you need.

The nice thing about this is that all oscillator transistors are clicking right into saturation, so process can get very very bad before you stray too far from perfect.

Do you need a sine? what's your application?

 

[morecode1234567890]

ok. thx to all for your answers.
are There any book o ebook that contains information about oscilators?

thx again

 

[andy2000a]

from my experience , simulation OSC

1. simulation phase & gain
2. make sure your spice model is ok ..

a few year ago , I use tsmc 0.5u spice model , but the invert gain
is very strange .. finally I think the problem is spice model issue
becuase we can find W/L select in spice model

like W/L = 10/1 select N.1
W/L = 20/1 select N.2

but in spice simulation , spice model have section region cause spice
not continue , and cause simulation have strange "Gain"

but only some case .. so I omit this error simulation ..
by the way , osc design should be notice Xtal/resnaort model ..
or add some damping resistor remove OSC noise ..

I also hope I can try neoCircuit .. but this tool too expensive ..
and not linux or windows demo version ..

 

[electronrancher]

that W/L selection should be no problem - it's used often by foundries to show differences that are not modelled in bsim3 or spice level xx.. actually, if you have models that select based on W/L they are probably made very well.

i have made several oscillators that sim fine and work pretty much the same in silicon - not sure what the problems you guys are seeing are due to..

 

[andy2000a]

Hi
I simulation a Invert (OSC gain stage )
normal case gain =10 (not db)
but some case gain=1000 ---> I don't believe it ..

this is 5 year ago case.... maybe it cause by hspice , not TSMC model
but I am not sure .