I have once spent quite some time in designing a ringsocillator used in a PLL in 0.35 um CMOS. You must *always* see to that the ring gain is larger than one. Otherwise your design will be a disaster since it won't oscillate. Therefore you must simulate for the worst conditions regarding gain (which was process corner WS, max temperature for me).
Also, the frequency of the oscillator will very much be dependent on the process corner, temperature and component tolerances. The ringoscillator design idea is a nice one, but it produces much noise. Therefore you must see to that the output impedance of each stage is low, which brings about large capacitors, which consumes space on the chip.
To use a filter is also an idea to make the output signal more sinus-like, however, the breakpoint frequency of the lowpass filter must be about the same as the nominal output signal's frequency, which leads to that the output signal's amplitude after the lowpass filter will very much depend on the oscillator's frequency.
I managed to solve the main problems by using feedback/feedforward loops in the signal chain between the different stages (lowered the distortion), and amplitude compensation that was controlled by the frequency controlling signal. But it was very difficult to optimize the whole circuit regarding process corners, temperature, supply voltage variations, component tolerance (especially resistors). I used Cadence IC 4.4.3 for the simulations and sure I would have wished that I had Neolinear Neocircuit too (Neocircuit is a automatic optimization program, if anyone has it, please drop me a PM
).
I wish you good luck.
/Pim
morecode1234567890 said:
I am simulating a ring oscilator in typ conditions, when i change the librarys that make typ conditions, worst case, the gain of each stage y lower than 1 so I lose my signal. If the design is modified for work in that conditions, the gain in the circuit is very high, so the signal is not sin as i need it. Have you any idea.
Sorry for my english.
Thx in advance.