Hi,
I want to try and get both voltages from 1% to 0.1% matched. "Or more".
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Hi,
Again: what is this good for?
Klaus
Matched? Matched to what?
It seems you don't know what you are talking about.Analog is slow, H bridge is expensive, and complex.
betwixt said:What are the red and green LEDs for?
It would help if you showed your proposed schematic with the 75176 as part of the diagram instead of using ambiguous names for the signals.
I'm well aware of those effects (Audio designer, mathematician). Tho I did harm the integrity (symmetry under load) of my build by doing the diode thing.Audioguru said:The datasheet for the SN75176 shows on graphs fig1 and fig2 that the output high voltage loss is very different to the output low voltage loss and they cannot be matched like you want.
A squarewave sounds like a buzzer. The duty-cycle of the high time to the low time determines how much even harmonics are added to the odd harmonics of a squarewave. With audio frequencies and higher, both LEDs will light the same and will look like they are both turned on together. Changing the duty-cycle with Pulse Width Modulation (PWM) increases the brightness of one LED while it dims the other LED.
The problem is when I do this, the leakage voltage between the added PSU + and - potentials is going to erase the driver being at 0.Adding a pullup resistor to one side and a pulldown to the
other (plus, minus) will give you a DC imbalance. Used to
do this to "crutch" the failsafe operation of line receivers
when customers insisted on interposing series resistors
between the line and input pins (degrading the open circuit
failsafe margin).
The common mode offset should be a don't-care. Differential
skew is going to make a bit of duty cycle distortion out the
back of the receiver (but if the transmission line and the
driver edges are crisp, not much effect until you get to near
minimum overdrive for functionality).
I had a look at the datasheet. There are two charts for output characteristic HIGH and LOW.The goal is to see if I can make a ladder DAC for my FPGA
But for varying load I´d say it is impossible.with performance under a varying load
Yes, I think it's getting very hard.But for varying load I´d say it is impossible.
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