Nixphe
Junior Member level 1
Hello,
I tried to make an integrator in veriloga. Using the idt function (out = idt(in, 0), this is very easy. Then i wanted to limit the integrator to 0V at the lower side and to 1V at the upper side. This proved to be a lot harder than i thought.
I had:
out = idt(in, 0);
out = (out>1)? 1ut;
out = (out<0)? 0ut;
The limiting part works, but apparently clipping variable "out", does not clip the integral.
Then I started experimenting with 2 things, one is the assert option, the other is to change the "in" variable when out of range, i.e.:
if ( ((out>1)&&(in>0)) || ((out<0)&&(in<0) )
in = 0;
out = idt(in, 0);
This kind of works. I expected the output to go little over the boundaries, but i was quite surprised to see out rising up to 1.5 or even 2.
How can i solve this? What's the reason of this problem?
Thanks in advance!
I tried to make an integrator in veriloga. Using the idt function (out = idt(in, 0), this is very easy. Then i wanted to limit the integrator to 0V at the lower side and to 1V at the upper side. This proved to be a lot harder than i thought.
I had:
out = idt(in, 0);
out = (out>1)? 1ut;
out = (out<0)? 0ut;
The limiting part works, but apparently clipping variable "out", does not clip the integral.
Then I started experimenting with 2 things, one is the assert option, the other is to change the "in" variable when out of range, i.e.:
if ( ((out>1)&&(in>0)) || ((out<0)&&(in<0) )
in = 0;
out = idt(in, 0);
This kind of works. I expected the output to go little over the boundaries, but i was quite surprised to see out rising up to 1.5 or even 2.
How can i solve this? What's the reason of this problem?
Thanks in advance!