Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Library not found error message + VCS

Status
Not open for further replies.

dpaul

Advanced Member level 4
Joined
Jan 16, 2008
Messages
1,473
Helped
307
Reputation
614
Reaction score
301
Trophy points
1,373
Location
Germany
Activity points
11,020
I have a Xilinx VHDL IP which I am compiling along with other Verilog and SV design files. I am compiling the VHDL design files first.
Prior to compiling the VHDL design files, I have compiled the Xilinx VHDL libs using the command:
compxlib -s vcs -p /home/shared/Synopsys/I-2014.03-SP1/bin/ -arch spartan6 -dir /home/dpaul/rtl_work/xilinx_vhdl_libs -l vhdl -lib all -log /home/dpaul/rtl_work/xilinx_vhdl_libs_compile.log

In the vhdlan command I also using the switch -smart_order

Still I am getting the following error:
Code:
Error-[OVNOSELECT1_LIB] Undefined identifier
/home/dpaul/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/proc_common_v3_00_a/srl_fifo_rbu2_f.vhd, 256
IMP
        DYNSHREG_F_I : entity proc_common_v3_00_a.dynshreg2_f
                                                ^
  The symbol named 'DYNSHREG2_F' cannot be found in library   'PROC_COMMON_V3_00_A'.

I have cross checked that logical and physical lib mapping for PROC_COMMON_V3_00_A exists in the synopsys_sim.setup file.

Not only this I am also compiling the dynshreg2_f.vhd file before compiling srl_fifo_rbu2_f.vhd.

Here's part of the code where the error occurs:
Code:
library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.UNSIGNED;
use     ieee.numeric_std.">=";
use     ieee.numeric_std.TO_UNSIGNED;
library proc_common_v3_00_a;
use     proc_common_v3_00_a.proc_common_pkg.clog2;

entity srl_fifo_rbu2_f is
  generic (
// generics
    );
  port (
   // ports
    );
end entity srl_fifo_rbu2_f;


architecture imp of srl_fifo_rbu2_f is

  .
.
.
.
begin
.
.

    ----------------------------------------------------------------------------
    -- The dynamic shift register that holds the FIFO elements.
    ----------------------------------------------------------------------------
    DYNSHREG_F_I : entity proc_common_v3_00_a.dynshreg2_f   <-- ERROR HERE!
        generic map (
            C_DEPTH   => C_DEPTH,
            C_DWIDTH  => C_DWIDTH,
            C_FAMILY  => C_FAMILY
        )
        port map (
            Clk   => Clk,
            Clken => FIFO_Write,
            Addr  => addr_i(ADDR_BITS-1 downto 0),
            Din   => Data_In,
            Dout  => Data_Out
        );
.
.

What could I do here?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top