Level shifter from 1.0 V to 3.3 V maximum speed

[IADanilov]

I'm designing level shifter from 1.0 V to 3.3 V in 65 nm CMOS process. I have tuned and simulated various types of circuits with zero static power consumption. But all of them have maximum operating frequency below ~200-300 MHz. Is it even possible to design a circuit with zero static power consumption which can operate at least at 500 MHz?

 

[allanvv]

Are you sending this signal out externally? It's probably a difficult task because other commercial chips like high-end FGPA's don't support high frequency 3.3V CMOS.

 

[dick_freebird]

I've done 3.3V SOI static dividers to over 1GHz but JI
has a lot more capacitance.

A question to ask yourself is, just how far and into what
kind of load do you imagine you're going to throw that
500MHz, full-swing-CMOS signal?

Because a 10mA buffer and a 5pF load, probably isn't
going to achieve close to full swing in a 1nS half-cycle.

Maybe you really want to be designing a high speed LVDS
buffer, or PECL, or something. But these are of course
not zero static power.

Now, you ought to run some calcs based on the driven
load and pin activity, and see whether zero static power
is really any kind of relevant - or what a reasonable
static power might be, that still didn't matter in the big
picture. That might free your hand, some.

 

[IADanilov]

Maybe you really want to be designing a high speed LVDS
buffer

It is just the case. So, load is very small and distance is very short.

But these are of course not zero static power.

You mean whole LVDS buffer or just level shifter circuit?