There are level shifter parts in the 74xxx family. They may
have poor TPLH/TPHL symmetry. Perhaps something like a true
differential line driver, with some voltage gain (say, A=2), is
more what you want. If your clock is under 1GHz a current-
feedback amplifier could likely hang with it, there are some
pretty sporty ones out there.
Now I'm not seeing why the ADC must be clocked by the
FPGA other than simplicity. Maybe you would be better off
clocking the ADC with what it wants, and letting the FPGA
see an image of that clock.
That's a fairly long cable, what data rate do you think you
can throw down it with (evidently) CMOS logic drivers?