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From my experience of using both synthesisers for large designs, I firmly believe that Synplify is the "Poor man's" synthesiser, and Leonardo is the superior product.
Synplify have pursued a "click once" synthesise strategy, which means that the software makes lots of assumptions for you. This is fine for small designs, and may be why beginners find it more approachable, but large designs are unavoidably complicated, and as an engineer I need visability and control over that. I'll give you an example - I did one design that took up a large chunk of an XC2V3000 FPGA, and I had scripts for building it under both synplify and Leo. After one small design change, the Synplify version stopped working, and the Leo version was fine. After a lot of searching I found that Synplify had arbitrarily decided to change the timing characteristics of my IOs because the design had crossed some invisible size threshold. This is not the kind of decision a synthesiser should make on its own - it stopped my carefully constructed SRAM interface from working.
Another reason I dislike Synplify - it requires synthesise constraints to be embedded in the code. This makes a joke of VHDL being architecturally-independant. Those kind of constraints belong in constraints file of some kind. I've never had to dirty my code with synthesiser-specific constraints when using Leo.
Leo does a much better job of infering ram than synplifiy (hey - more code-embedded synthesiser constraints required for synplifiy!), and since I use a lot of RAM this makes my job much easier.
Synplifys error and warning reporting is absolute rubbish - next to no use at all. A friend of mine is required to syntesise his designs with synplify, but he actually develops the code with Leo because of its superior error/warning output.
In terms of actual synthesiser performance there's not much in it between them - Leo's maybe a little better for really big designs, but not by much.
And in favor of synplify - the EDIF schematic browser is much better, and it's cheaper.
I have worked a lot of years with Leon@rdo and last year I started with Synpl!fy.
There are quite a lot of differences of course. Synpl!fy GUI is better, the schematic viewer is better, the navigation is better. The FSM extraction is good and is not supported in Leon@rdo.
Both are fast.
In Leon@rdo you can get a free version for Alter@ devices but not for Synpl!fy.
I HATE one thing in Synpl!fy, sometimes you have to modify your VHDL/Verilog code to make life easier for Synpl!fy. You have to add the "syn_" attributes and that is really annoying. Imagine you are modifying and old design which was synthesized using Leon@rdo and now your company only supports Synpl!city Corporate Licenses, that means you have to modify your VHDL to get your design synthesized properly.
Synpl!fy is clock driven, Leon@rdo is not that strict ni that aspect.
One think I really like about Leon@rdo, PRESERVING HIEARACHY. This is good to give you a rough idea of the amount of logic used for every single block in your design. It is usually better to flatten your design but this option is there.
There are more thoughts, this is a list of things to have in mind.