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yes Jaydip , the LEC have the classify of Extra and unreachable .
there are include two question ,
1. if these Dlatch is not RTL , then why LEC didnot classify them to be Extra .
2. why the D_latch of clock gating is unreachable ? (that is why them can't observe or not affect the output ?)
As clock gating cell is only present in netlist. Using set flatten model -gated_clock in LEC dofile make it unreachable. Basically it converts or model netlist and make mux feedback structure on revised side too ,which then become same as on golden side. Now as the CG cell is no more in the clock path of flop(virtually),So it becomes unreachable.
thanks all for reply ,
now in my understand , I think the reason is using
option of 'set flatten model -gated_clock' , it will remodel the clock gating logic in netlist , convert the logic be same as RTL , then the D-latch be deleted (or convert as combinational logic), so it have no obseve point (not ff ,not PO, not keypoint) , so it be classified in unreachable .