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LEC unreachable point for dlatch of clock gating

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Junior Member level 1
Apr 19, 2007
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lec unreachable

Hi , why LEC assume the D-latch of clock gating be unreachable point ?
why can't observe the output of the D-latch ?
thanks .

clock gating d latch unreachable

clock gating is present in your netlist only.. you dont have clock gating in your RTL design (verilog) ... this means in RTL, latch is unreachable because it is not present at all in RTL . ..

hope it helps ..

gating be

thanks jaydip, but , as your description , these latch should be classified to Extra ...

set flatten model -gated_clock

dont have access to LEC documentation .. so cant comment .. can you check it over there ?? formality does not classify points as extra or unreachable, I guess ...

clcok gating

yes Jaydip , the LEC have the classify of Extra and unreachable .
there are include two question ,
1. if these Dlatch is not RTL , then why LEC didnot classify them to be Extra .
2. why the D_latch of clock gating is unreachable ? (that is why them can't observe or not affect the output ?)

lec extra revised

Hi Jaydeep,
As clock gating cell is only present in netlist. Using set flatten model -gated_clock in LEC dofile make it unreachable. Basically it converts or model netlist and make mux feedback structure on revised side too ,which then become same as on golden side. Now as the CG cell is no more in the clock path of flop(virtually),So it becomes unreachable.

Hope it clears.


clock gating

u have to model the clockgating in lec to make understand tool about the cg latches

clock gating latch

thanks all for reply ,
now in my understand , I think the reason is using
option of 'set flatten model -gated_clock' , it will remodel the clock gating logic in netlist , convert the logic be same as RTL , then the D-latch be deleted (or convert as combinational logic), so it have no obseve point (not ff ,not PO, not keypoint) , so it be classified in unreachable .

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