LEC and clock gating

[sun_ray]

How can clock gating insertion creates mismatch in LEC?

Regards

 

[rca]

no pb for LEC, because the tool found that the clock gating is inserted on the clock nets, LEC compare memory element (flop) and I/O.

 

[sun_ray]

no pb for LEC, because the tool found that the clock gating is inserted on the clock nets,.

There will be problem and hence this thread was started.

no pb for LEC, because the tool found that the clock gating is inserted on the clock nets, LEC compare memory element (flop) and I/O.

Regards

Do you want to mean LEC do not compare combinatorial logic?

 

[rca]

LEC checks the combinational logic, but it is enought intelligent to detect the logic used for the gating clock comes from the gating data.

 

[englishdogg]

If your referring to an RTL to netlist compare the rtl will not have clock gates and the netlist will have. in such a case LEC does gated_clock modelling and then does the compare to ensure that both sides now are same. IN this case issues can occur if modelling executed is not correct.

Although i have not witnessed such a case yet.