Sep 21, 2014 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Hello, When instantiating a VHDL component, sometimes Modelsim doesn't allow to leave output ports OPEN while in other cases it does allow that. What is the rule according to the LRM ? When is it allowed to leave a component output port OPEN?
Hello, When instantiating a VHDL component, sometimes Modelsim doesn't allow to leave output ports OPEN while in other cases it does allow that. What is the rule according to the LRM ? When is it allowed to leave a component output port OPEN?
Sep 21, 2014 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 You can always leave an output port open, unless it is unconstrained.