leaving a VHDL port open

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shaiko

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Hello,

When instantiating a VHDL component, sometimes Modelsim doesn't allow to leave output ports OPEN while in other cases it does allow that.

What is the rule according to the LRM ?
When is it allowed to leave a component output port OPEN?
 

You can always leave an output port open, unless it is unconstrained.
 
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    shaiko

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