leaving a VHDL port open

[shaiko]

Hello,

When instantiating a VHDL component, sometimes Modelsim doesn't allow to leave output ports OPEN while in other cases it does allow that.

What is the rule according to the LRM ?
When is it allowed to leave a component output port OPEN?

 

[TrickyDicky]

You can always leave an output port open, unless it is unconstrained.