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Leakage power reduction

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kumar_eee

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What are all the methods you use during the leakage power optimization other than Vt swapping?
 

phoenixpavan

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Hi Kumar,

we can perform the following methods for Power opt

Supply voltage reduction
clock gating(dynamic power reduction)
Multi Vt
Mutivoltage design(using level shifter cells)
Power switching(using isolation cells and retention registers)
DVFS(dynamic voltage and frequency scaling)


cheers,
 

kumar_eee

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Hi Pavan, Thanks a lot. I'm specifically looking for the leakage power optimization methods.
 

divya ravi

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Methods for leakage power optimization are
1. Reducing Threshold Voltage(Vt)
2. source biasing
3. body biasing
 

dineshrayar

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hi..
if u reducing Vt means.. the leakage power will increase.. so if u want to reduce leakage power u have to go for high Vt cells or MTCMOS, variable Vt CMOS, multi VDD design or power gating methods.. basically in high freq design dynamic power dissipation will be more n leakage will be less... there will be lot of tradeoffs b/w leakage/dynamic power, freq and no of Vdd's....
 
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kumar_eee

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presently I use HVT cells to reduce the leakage power. Does std cell library contains the MTCMOS cells also?
 

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