First of all, how can you know "the current in the Pmos is reversed so the tool is rounding off the -ve current value to 0", have you checked the pmos leakage current in accumulation mode. Or checked the leakage current of the nmos?
Which nodes are you using? According to my experience, the leakage current for older CMOS process (>= 180nm) is extremely small and I am not surprised you see 0 leakage current.
Also, I remember there is a switch about gate leakage current in the transistor parameter file. If the switch is off, the simulator will skip gate leakage current simulations.