Leakage measurement Pmos decap ( Inversion mode)

[maxy_spy]

Hello everyone,
I am trying to figure out how to measure the Leakage current in the Pmos Decap.
PMOS --> gate to VSS, other three nodes to VDD ( inversion)

The problem I am facing right now is that the current in the Pmos is reversed so the tool is rounding off the -ve current value to 0.

I am trying to find a method to calculate the leakage and Q factor in this type of decap.

Please provide me your inputs.

Thank you

 

[mohmohcha]

First of all, how can you know "the current in the Pmos is reversed so the tool is rounding off the -ve current value to 0", have you checked the pmos leakage current in accumulation mode. Or checked the leakage current of the nmos?

Which nodes are you using? According to my experience, the leakage current for older CMOS process (>= 180nm) is extremely small and I am not surprised you see 0 leakage current.

Also, I remember there is a switch about gate leakage current in the transistor parameter file. If the switch is off, the simulator will skip gate leakage current simulations.

 

[dick_freebird]

I have yet to encounter a MOSFET model which had any
gate leakage attempt, let alone accuracy. Leakage in the
thicker oxides is defect driven. Only when you get to the
thickness range where tunneling (or percolation, but that
tends to not be reliable / qualifiable, there you get wearout)
becomes significant can you model all devices as having a
similar baseline gate current.

I do not know what node that's at.

You can calculate a worst case (room temp) number from
PCM accept limits in the BVOx or gate ox leakage tests if
you know the test device geometry and your geometry-
of-interest. This might suffice for figuring supply current
impact of decoupling elements, even if it's absurd 99.9%
of the time.