Leakage Current for mosfet

[zarric]

the circuit shows below

when LVNMOS is off, simulation result shows that the voltage at point A is high than HVNMOS gate voltage and even exceed the breakdown voltage of LVNMOS.

whether the circuit works as simulation ??[/img]

 

[DenisMark]

Hello Zarric,
Yes, it really can happen. And it can also take place during ESD zap when capacitance coupling between HV and A strong enough. Also ever if HVNMOS is used instead of LVNMOS it won't solve an issue of this circuit because there is still a risk to damage gate-source oxide of top HVNMOS.
You have to remove this potential weakness of circuit in all places. The common practice is to clamp potential on node A:
1) To use zener, diode connected MOSFET (depends from expecting voltage on A) between A and GND.
2) To use PMOS, source to A, drain to GND, gate to LV.