hi. how to implement leading edge blanking circuitry in SG3526 pwm chip which has two outputs. it has to be operated in fullbridge with current sense resistor at bottom side.
In designing other Unitrode-compatible PWMs I recall this being an internal feature
without much user access. Idea being to prevent false early end-of-cycle from
switch ringing (but getting the ringing to damp within LEB window, is on you).
Hmm, I don't see any way to implement it on that controller. It doesn't give any user access to the logic controlling the internal latches. If you absolutely need blanking, then you should find another controller that offers it.
edit: well, to clarify there are ways to effectively get LEB, but it has to be done by modifying the current sense signal, rather than the internal state machine. Basically you just need to inject a pulse into the input of the CS comparator at the start of each switching cycle. It's kind of messy, but if you're interested then I can go into detail.
well, to clarify there are ways to effectively get LEB, but it has to be done by modifying the current sense signal, rather than the internal state machine. Basically you just need to inject a pulse into the input of the CS comparator at the start of each switching cycle. It's kind of messy, but if you're interested then I can go into detail.
Another very interesting discussion that I found on LEB at TI website is linked below. the attached pdf and discussion below is for single gate drive like UC3844. however for SG3526 which has two pulses per period it looks messy to make two circuits for each gate drive.