LDO transient response 0.1ns rise and fall time

[hdkwan]

LDO transient response

Hi all,

I am trying to design an 1A LDO. I am using 0.1ns rise and fall time for my load transient. Is the time too short? Is there any application that has 0.1ns rise and fall time?
Thanks.

 

[karesz]

LDO transient response

Hi,
of course.
I mean, in my opinion you have to select 0.1 usec for a voltage regulator...
For LDO is (my be)even more real to set 0.1 msec.

Your 0.1 nsec=ca. 3GHz as 3dB in system, but means in signal theorie sooner a Bw of ca.- 10 GHz...
Not so direct that what you wishes?

Good luck!
K.

 

[hdkwan]

Re: LDO transient response

I am trying to design a fast settling LDO. The settling time should be around 100ns (0.1us).
I feel that if the load transient itself is much slower than the settling time, the measured settling time may not be correct.

Where do you get the 3GHz figure?

 

[karesz]

LDO transient response

Hi hdkwan,
Take the practical formel:
0.35 divided by your edge time (you wrote first 0.1nsec!) = Fbw to 3dB_ this is my source
Greatings!
K.

Added after 3 minutes:

Overthink your golas eventually please, this isnot an LDO, this is more A HIGH FREQUENCY POWER AMP w. TIGHT SPECS!
You selected a very hard way for you, and if it must not be a "must have"- why than?...
K.

 

[hdkwan]

Re: LDO transient response

0.35 divided by your edge time (you wrote first 0.1nsec!) = Fbw to 3dB_ this is my source

I never see this formula, where do you get this?



in the ieee paper titled "An Improved Fast Transient Response Low Dropout
Voltage Regulator" by Mohammad Usaid Abbasi

They are using 1ns rise and fall time with 44ns settling time...

 

[dick_freebird]

LDO transient response

In that timescale, you would depend on the external filter /
decoupling components to keep the output stiff. There
is no way your loop amplifier is going to slew meaningfully
in that timeframe (0.1nS).

Modeling your decoupling elements well, is important. You
should not design against ideal capacitors because you will
not have them on the board. Though you should ensure
that unreasonably ideal elements don't cause trouble,
it will probably help you in the end to have good lumped
RLC capacitor subcircuits.

 

[karesz]

Re: LDO transient response

0.35 divided by your edge time (you wrote first 0.1nsec!) = Fbw to 3dB_ this is my source

I never see this formula, where do you get this?...

They are using 1ns rise and fall time with 44ns settling time...

Its an knowed practical formel(moves betw. 033-0.36) _I know it over tenth of years; may be you can it refind in handbooks...

Can you upload (or send me) your IEEE script pls?
Tnx & greatings!
K.

 

[hdkwan]

Re: LDO transient response

I never see that kind of formula before... lol...
I'm still an undergrad student... hehehehe

Added after 1 minutes:

0.35 divided by your edge time (you wrote first 0.1nsec!) = Fbw to 3dB_ this is my source

I never see this formula, where do you get this?...

They are using 1ns rise and fall time with 44ns settling time...

Its an knowed practical formel(moves betw. 033-0.36) _I know it over tenth of years; may be you can it refind in handbooks...

Can you upload (or send me) your IEEE script pls?
Tnx & greatings!
K.

sorry, i read the result wrongly. it was 44ns faster than another design. not 44ns settling time... hhehehe.

 

[karesz]

LDO transient response

Hi, I found it yesterday_absolute randomly_ in these book:
Allen Hollister: Wideband Amplifier Design, 2007, ISBN: 9781891121517, pp10-12...
K.