I am trying to design an 1A LDO. I am using 0.1ns rise and fall time for my load transient. Is the time too short? Is there any application that has 0.1ns rise and fall time?
Thanks.
I am trying to design a fast settling LDO. The settling time should be around 100ns (0.1us).
I feel that if the load transient itself is much slower than the settling time, the measured settling time may not be correct.
Hi hdkwan,
Take the practical formel:
0.35 divided by your edge time (you wrote first 0.1nsec!) = Fbw to 3dB_ this is my source
Greatings!
K.
Added after 3 minutes:
Overthink your golas eventually please, this isnot an LDO, this is more A HIGH FREQUENCY POWER AMP w. TIGHT SPECS!
You selected a very hard way for you, and if it must not be a "must have"- why than?...
K.
In that timescale, you would depend on the external filter /
decoupling components to keep the output stiff. There
is no way your loop amplifier is going to slew meaningfully
in that timeframe (0.1nS).
Modeling your decoupling elements well, is important. You
should not design against ideal capacitors because you will
not have them on the board. Though you should ensure
that unreasonably ideal elements don't cause trouble,
it will probably help you in the end to have good lumped
RLC capacitor subcircuits.