LDO linear regulator output problem

[FreshmanNewbie]

I am using this LDO

• Input Voltage is 14V
• Output Voltage is 5V
• Maximum Load Current is 150mA

Schematic :

I am observing two problems:
Problem 1:
Initially when I power on the LDO by given the input voltage but I am not providing an ENABLE signal to the LDO, I am getting a voltage of 2.65V at the LDO output for 5 seconds. Please see the below waveform.

Can someone tell me why this is happening? I am not able to find anything related to this in the datasheet.
Problem 2 :
This below test was done in thermal oven at a temperature of 95degC. The junction temperature of the IC would be even higher than 95degC. I give a transient pulse from 16V to 18V for some 400ms and then back to 17V for some 600ms and the back to 16V. I give 3 pulses like this. The rise time and fall time of the pulse transitioning from 16V to 18V and then back to 16V is 1ms only. When I give this pulse at the LDO input, the output voltage 5V goes to 0V like shown below. The current was stable at 150mA but when this pulse is applied, it goes above 350mA and then to 0A and oscillates as shown below. Can someone tell me why this is happening?
I checked the LDO datasheet, but I was not able to find anything regarding this.

The above same test when done at 25degC:

 

[betwixt]

What are R3401/R3402/C3405 for and why do you have two capacitors in series across the input?
The suggest values are 10uF and 100nF in parallel across the input and 1uF across the output.

Brian.

 

[Pjdd]

Those questions immediately came up in my mind when I first saw the schematic.
The problem looks like an instability of some kind. The circuit looks fine except for those peculiarities. The layout may have something to do with it but we won't know unless the OP posts a photo.

 

[d123]

Hi,

1) Without knowing what's attached to enable pin...:

Maybe use a pull-down resistor on enable pin if it is active high, or vice versa if it is active low.

It might be floating at power-up and so output goes high momentarily until it settles and goes low. That would charge the output capacitors - until the output capacitors drain, there will be a (residual) voltage present at Vout.

Maybe.

2) There may be a sentence in the datasheet mentioning output capacitors and stability or claiming stability with x value or unconditional stability, or some reference to an app note for the part?

Agree with previous two posts - Why that resistive divider and capacitor at output, and series caps at input?

 

[Pjdd]

I had a look at the datasheet. The Enable pin is active high and has an internal pull-down resistor. It also says that there's no need for an input capacitor and that the IC is stable with output capacitors with ESR less than 5 ohms.

 

[treez]

TLS715 datasheet

TLS715B0 datasheet

Download TLS715B0 pdf datasheet file

datasheetspdf.com

..did you accord with page 4 concerning enable? Pg4 says Cin is needed, right close to terminals.
Is your cout right close to terminals?

 

[KlausST]

Hi,

The pulldown of the Enable is very high ohmic. Noise may cause malfunction.

Klaus

 

[pjmelect]

Are you sure you have a genuine LDO? Many cheap LDO's from China are fake and exhibit strange behaviour or breakdown with higher supply voltage.

 

[FreshmanNewbie]

What are R3401/R3402/C3405 for and why do you have two capacitors in series across the input?
The suggest values are 10uF and 100nF in parallel across the input and 1uF across the output.

Brian.

Thank you for the comment. The 2 resistors actually form a voltage divider network which is fed to the ADC Pin of the microcontroller, so as to have a track of the output voltage. The Capacitor is placed to reduce the glitches. I have removed this portion from the image because I didn't suspect that this might be a reason for the problem which I am facing. I apologize for this.

The Input capacitor are added of that value so that they can help with the input voltage glitches and spikes of very small magnitude and help to smoothen the input voltage. Actually, I have a input capacitor value of 150uF on the input pin of the LDO which is not shown here as it is placed on a different location in the schematic. The idea of these capacitors is to handle brief momentary power supply interruptions and help to maintain the output.

I am mainly concerned about the Enable pin and the input voltage pin.

How, with no enable signal, how does my output go high for sometime like 5 seconds. I couldn't find anything related to this in the datasheet.

Is there any relation of between the input voltage pin and the enable pin (I am asking like, is there any circuit which is connected from the input voltage pin to the Enable pin)

To cross verify this Enable signal behaviour, I have lifted the Enable IC pin from the PCB and gave a 5V power supply to the Enable pin using a very thin and a short copper wire. Still the same behaviour. I am not sure, how this event is happening for a long period of 5 seconds?

--- Updated Jul 18, 2020 ---

Those questions immediately came up in my mind when I first saw the schematic.
The problem looks like an instability of some kind. The circuit looks fine except for those peculiarities. The layout may have something to do with it but we won't know unless the OP posts a photo.

Thank you for the comment. Regarding the reason for the resistors divider network and the capacitors, I have mentioned the reasons in the post #9. Please check and provide your help.

And all the input and the output capacitors are placed closed to the IC pins. What problem are you suspecting in the layout?

--- Updated Jul 18, 2020 ---

Hi,

1) Without knowing what's attached to enable pin...:

Maybe use a pull-down resistor on enable pin if it is active high, or vice versa if it is active low.

It might be floating at power-up and so output goes high momentarily until it settles and goes low. That would charge the output capacitors - until the output capacitors drain, there will be a (residual) voltage present at Vout.

Maybe.

2) There may be a sentence in the datasheet mentioning output capacitors and stability or claiming stability with x value or unconditional stability, or some reference to an app note for the part?

Agree with previous two posts - Why that resistive divider and capacitor at output, and series caps at input?

Thank you for the comment. I have mentioned my reasons for the resistor divider and the capacitor on post #9. Please check and provide help.

The datasheet of the LDO mentions that the Enable pin has an integrated pull-down resistor. So, why is this problem occurring? And why do you recommend to add another pull-down resistor at the enable pin? Please advice

--- Updated Jul 18, 2020 ---

TLS715 datasheet

TLS715B0 datasheet

Download TLS715B0 pdf datasheet file

datasheetspdf.com

..did you accord with page 4 concerning enable? Pg4 says Cin is needed, right close to terminals.
Is your cout right close to terminals?

Yes, I have placed the capacitors as close as possible to the input terminals.

--- Updated Jul 18, 2020 ---

Hi,

The pulldown of the Enable is very high ohmic. Noise may cause malfunction.

Klaus

Could you please explain how the high ohmic resistor will cause this behaviour? And which noise and at which place on the IC will cause this malfunction?

--- Updated Jul 18, 2020 ---

Are you sure you have a genuine LDO? Many cheap LDO's from China are fake and exhibit strange behaviour or breakdown with higher supply voltage.

Yes, I have made sure that this is a genuine LDO.

 

[KlausST]

Hi,

Why don't you show your PCB layout?
Why not the complete schematic ... including input capacitor?

High ohmic Enable pullup:
Imagine externally coupled erroneous noise signals as "current"
Say the coupled signal 10uA. Now with a pullup if 1.5MOhm you get an erroneous voltage shift by 15V (theoretically, if not limited otherwise)
If there is a pullup of 10kOhm, then the same 10uA cause just a voltage of 100mV.

Less voltage, less malfunction.

Klaus

 

[treez]

Tie the enable pin high right next to the regulator.....EG Avoid using big loop of wire which will pick up noise into the enable pin.
Did you take all ESD precautions in handling?

 

[FreshmanNewbie]

Hi,

Why don't you show your PCB layout?
Why not the complete schematic ... including input capacitor?

High ohmic Enable pullup:
Imagine externally coupled erroneous noise signals as "current"
Say the coupled signal 10uA. Now with a pullup if 1.5MOhm you get an erroneous voltage shift by 15V (theoretically, if not limited otherwise)
If there is a pullup of 10kOhm, then the same 10uA cause just a voltage of 100mV.

Less voltage, less malfunction.

Klaus

Thank you for the comment.

Regarding sharing the PCB layout and the schematic, I actually thought those might not be required as the problem might not be that.

But one thing regarding the the - High Ohmic Enable pullup : I have captured the enable signal in the scope waveform also. There is no voltage built-up on the enable line. It is 0V only. Then, how this is possible?

--- Updated Jul 19, 2020 ---

Tie the enable pin high right next to the regulator.....EG Avoid using big loop of wire which will pick up noise into the enable pin.
Did you take all ESD precautions in handling?

Why should I tie the enable pin to high? My question is without the Enable pin high, my output goes High for sometime.

For my actual function, I don't want to enable to output for the initial few seconds.

Yes, I took necessary ESD Precautions.

 

[treez]

..Read page 4 of datasheet....it wont work unless you tie the enable pin high.

High means above 2v.

I think this is your problem.

 

[KlausST]

Hi,

But one thing regarding the the - High Ohmic Enable pullup : I have captured the enable signal in the scope waveform also. There is no voltage built-up on the enable line. It is 0V only. Then, how this is possible?

With this information I just see a couple if possible errors:
* wrong schematic (your schematic. The datasheet schematic mist probably is correct). Thus I again ask for your schematic.
* wrong PCB layout ...
* defective IC
* defective power supply
* wiring / soldering error.

Now please review your given informations. Are we able to verify a single point?

We want and we will help you. But we can't..

Klaus

 

[Pjdd]

Thank you for the comment. The 2 resistors actually form a voltage divider network which is fed to ............

I guessed this and the others probably did too. The question was asked out of curiosity, not really because it's suspected as the culprit.

The Input capacitor are added of that value so that they can help with the input voltage glitches and spikes of very small magnitude and help to smoothen the input voltage. Actually, I have a input capacitor value of 150uF on the input pin of the LDO which is not shown here as it is placed on a different location in the schematic. The idea of these capacitors is to handle brief momentary power supply interruptions and help to maintain the output.

There's nothing wrong with placing the capacitors at the input. Our questions were about using TWO capacitors C3402 and C3403 in series instead of just one.

And all the input and the output capacitors are placed closed to the IC pins. What problem are you suspecting in the layout?

Nothing specific. In fact, it's not possible to be specific until we've seen the layout. It's simply one possibility.

Have you tried another combination of capacitors? In real life, capacitors are complex devices with many parasitic elements. It's possible that the regulator doesn't like the ones you're using.

To sum up: there's no obvious reason why your circuit is behaving like this. There must be some less obvious reason and the possibilities have to be investigated. Some of these are the layout, capacitors, even the load.

 

[malli_1729]

As KlauST suggested, EN should have strong pull-down for testing purpose use 1K pull-down, EN only 5.5uA to change its state.
1. On Input pin 2 , 220nF capacitors are connected in series, why is that - Use only one capacitor (smaller/higher as required)

With your Input 14V to 5V @150mA dissipates 1.35W assuming best case RthetaJA as 75 k/W - this causes 101.25degC temperature Rise from Ambient.
You are saying testing @ Ambient of 95C - So, IC Tj will be 95+101.25 = 196C which already exceeded the Tj max.

You are using higher input voltage pulses up to 19V, with 19V to 5V @150mA will dissipate 2.1W which causes 157.5 degC temperature rise from Ambient.

None of these cases are in the recommended operating region of IC.
On 9th page there is some data on Protections
"Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited and the output voltage decreases.

The over temperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled, the regulator restarts. This oscillatory thermal behaviour causes the junction temperature to exceed the maximum rating of 150°C and can significantly reduce the IC’s lifetime "

 

[FreshmanNewbie]

As KlauST suggested, EN should have strong pull-down for testing purpose use 1K pull-down, EN only 5.5uA to change its state.
1. On Input pin 2 , 220nF capacitors are connected in series, why is that - Use only one capacitor (smaller/higher as required)

With your Input 14V to 5V @150mA dissipates 1.35W assuming best case RthetaJA as 75 k/W - this causes 101.25degC temperature Rise from Ambient.
You are saying testing @ Ambient of 95C - So, IC Tj will be 95+101.25 = 196C which already exceeded the Tj max.

You are using higher input voltage pulses up to 19V, with 19V to 5V @150mA will dissipate 2.1W which causes 157.5 degC temperature rise from Ambient.

None of these cases are in the recommended operating region of IC.
On 9th page there is some data on Protections
"Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited and the output voltage decreases.

The over temperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled, the regulator restarts. This oscillatory thermal behaviour causes the junction temperature to exceed the maximum rating of 150°C and can significantly reduce the IC’s lifetime "

Why should I have a strong pull-down? The Enable pin has an internal weak pull down. Isn't that enough?

 

[KlausST]

Hi,

It's already explained in post#10.

I don't like to guess. I'll be back when there is useful information...

Klaus

 

[malli_1729]

Why should I have a strong pull-down? The Enable pin has an internal weak pull down. Isn't that enough?

I explained these things in the above message itself, just check and specifically ask.
Try with Strong pull-down, If you want to remove that variable.
Some states it's hard to measure using DSO with general settings. Because we are not seeing any problem in scope captures doesn't mean there is no problem, it can be we are missing that event.

I clearly explained thermal problems - Concentrate on them first after adding strong pull-down.

 

[Akanimo]

The datasheet says on page 13 that the EN pin has to be connected to a voltage level of 0.8V maximum in order to switch the LDO OFF.

Use a strong pull-down as recommended in posts above.