Thank you for the comment. The 2 resistors actually form a voltage divider network which is fed to the ADC Pin of the microcontroller, so as to have a track of the output voltage. The Capacitor is placed to reduce the glitches. I have removed this portion from the image because I didn't suspect that this might be a reason for the problem which I am facing. I apologize for this.What are R3401/R3402/C3405 for and why do you have two capacitors in series across the input?
The suggest values are 10uF and 100nF in parallel across the input and 1uF across the output.
Brian.
Those questions immediately came up in my mind when I first saw the schematic.
The problem looks like an instability of some kind. The circuit looks fine except for those peculiarities. The layout may have something to do with it but we won't know unless the OP posts a photo.
Hi,
1) Without knowing what's attached to enable pin...:
Maybe use a pull-down resistor on enable pin if it is active high, or vice versa if it is active low.
It might be floating at power-up and so output goes high momentarily until it settles and goes low. That would charge the output capacitors - until the output capacitors drain, there will be a (residual) voltage present at Vout.
Maybe.
2) There may be a sentence in the datasheet mentioning output capacitors and stability or claiming stability with x value or unconditional stability, or some reference to an app note for the part?
Agree with previous two posts - Why that resistive divider and capacitor at output, and series caps at input?
TLS715 datasheet
..did you accord with page 4 concerning enable? Pg4 says Cin is needed, right close to terminals.
Is your cout right close to terminals?
Hi,
The pulldown of the Enable is very high ohmic. Noise may cause malfunction.
Klaus
Yes, I have made sure that this is a genuine LDO.Are you sure you have a genuine LDO? Many cheap LDO's from China are fake and exhibit strange behaviour or breakdown with higher supply voltage.
Thank you for the comment.Hi,
Why don't you show your PCB layout?
Why not the complete schematic ... including input capacitor?
High ohmic Enable pullup:
Imagine externally coupled erroneous noise signals as "current"
Say the coupled signal 10uA. Now with a pullup if 1.5MOhm you get an erroneous voltage shift by 15V (theoretically, if not limited otherwise)
If there is a pullup of 10kOhm, then the same 10uA cause just a voltage of 100mV.
Less voltage, less malfunction.
Klaus
Tie the enable pin high right next to the regulator.....EG Avoid using big loop of wire which will pick up noise into the enable pin.
Did you take all ESD precautions in handling?
With this information I just see a couple if possible errors:But one thing regarding the the - High Ohmic Enable pullup : I have captured the enable signal in the scope waveform also. There is no voltage built-up on the enable line. It is 0V only. Then, how this is possible?
I guessed this and the others probably did too. The question was asked out of curiosity, not really because it's suspected as the culprit.Thank you for the comment. The 2 resistors actually form a voltage divider network which is fed to ............
There's nothing wrong with placing the capacitors at the input. Our questions were about using TWO capacitors C3402 and C3403 in series instead of just one.The Input capacitor are added of that value so that they can help with the input voltage glitches and spikes of very small magnitude and help to smoothen the input voltage. Actually, I have a input capacitor value of 150uF on the input pin of the LDO which is not shown here as it is placed on a different location in the schematic. The idea of these capacitors is to handle brief momentary power supply interruptions and help to maintain the output.
Nothing specific. In fact, it's not possible to be specific until we've seen the layout. It's simply one possibility.And all the input and the output capacitors are placed closed to the IC pins. What problem are you suspecting in the layout?
Why should I have a strong pull-down? The Enable pin has an internal weak pull down. Isn't that enough?As KlauST suggested, EN should have strong pull-down for testing purpose use 1K pull-down, EN only 5.5uA to change its state.
1. On Input pin 2 , 220nF capacitors are connected in series, why is that - Use only one capacitor (smaller/higher as required)
With your Input 14V to 5V @150mA dissipates 1.35W assuming best case RthetaJA as 75 k/W - this causes 101.25degC temperature Rise from Ambient.
You are saying testing @ Ambient of 95C - So, IC Tj will be 95+101.25 = 196C which already exceeded the Tj max.
You are using higher input voltage pulses up to 19V, with 19V to 5V @150mA will dissipate 2.1W which causes 157.5 degC temperature rise from Ambient.
None of these cases are in the recommended operating region of IC.
On 9th page there is some data on Protections
"Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited and the output voltage decreases.
The over temperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled, the regulator restarts. This oscillatory thermal behaviour causes the junction temperature to exceed the maximum rating of 150°C and can significantly reduce the IC’s lifetime "
Why should I have a strong pull-down? The Enable pin has an internal weak pull down. Isn't that enough?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?