lcd interfacing in spartan 3E using vhdl

[Tetik]

The line "if clLK = '1' then" should be "if rising_edge(clLK) then "

You want to make a decision only when the clock toggles from '0' to '1'. Not always when clLK is '1' (this infer a latch).

 

[ads-ee]

I'd really like to know what VHDL book you've read or what VHDL websites you've visited, as I can't understand why you keep writing code the way you do. Perhaps you are visiting the wrong sites, ones written by VHDL newbies that don't really know how to write good code (which is the majority of the sites that exist).

I cringe every time I see variables used to generate counts, pipeline stages, etc. This usually means the VHDL writer thinks in terms of software design not hardware design. I usually end up throwing their code away and rewriting from scratch, which usually means the code is written for the device architecture and ends up running at a higher clock speed.

I recommend you don't use variables and for loops until you can actually write good VHDL code without either.

 

[p11]

**broken link removed**..

i have written the code from these site ...

 

[TrickyDicky]

You created a latch because you only check for clk = '1', not the rising/falling edge of the clock.

 

[wtr]

First we need to rewrite what you've posted with indentation & lets use syntax colouring so we can see how it looks
start with \[\syntax=vhdl\] & end with \[\/syntax] with where you remove the backslashes.

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity lcd is
    Port ( data : out  STD_LOGIC_vector (3 downto 0);
           lcd_rs : out  STD_LOGIC;
           lcd_rw : out  STD_LOGIC;
           lcd_e: out std_logic;
           clLk : in STD_LOGIC);
end lcd ;
 
architecture Behavioral of lcd is
 
 
constant N: integer := 13;
 
type arr is array (1 to n)of STD_LOGIC_vector (3 downto 0);
 
constant datas : arr := (x"3", x"2",x"8", x"0",x"8",x"0",x"1",x"0",x"6",x"0",x"c",x"5",x"0");
 
begin
 
  lcd_rw <= '0';
  
  process(clLk)
    variable i :integer :=0;
    variable j :integer :=1;
  begin
    if clLk ='1'  then
 
      if i <= 1000000 then
      
        i := i+1;
        lcd_e <= '1';
        data <= datas(j) (3 downto 0);
        
      
      elsif i >1000000 and i <2000000 then
      
        i:= i+1;
        lcd_e <= '0';
      
      elsif i = 2000000 then
      
        j := j+1;
        i:= 0;
      end if;
 
      if j <= 11 then 
        lcd_rs <= '0';
      elsif j > 11 then 
        lcd_rs <= '1';
      end if;
      
      if j =  13 then 
        j :=11;
      end if;
 
    end if;
  end process;
end behavioral;

---

For a start lets look at what latching is
https://www.doulos.com/knowhow/fpga/latches/

Try synchronising it with rising_edge(clLk)

 

[p11]

ok, thanks yes by using rising edge clk , this problem has been solved , but after writing the entire code , the lcd is displaying nothing , even the lcd is not getting on...

since fpga spartan 3e board supports 4 bit interface i have used the **broken link removed** for sending the codes for 4 bit interface . plz help me in realizing my faults. previously i did a project on 8051 microcontroller , i used lcd where i need to make sum switches on from the board . is there anything like that in this case ?

 

[kaiserschmarren87]

I read all the previous replies and tried myself to put the code in this order. I wrote an FSM for the code with a counter to keep track of the counting. The counter value is not specific here and I have used a sample. I have not completed it but thought this could be a solution. I hope it is correct.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.pkg_lcd.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity lcd is
 port (         data   : out t_data_array;
		  lcd_rs : out std_logic;
		  lcd_rw : out std_logic;
		  lcd_e  : out std_logic;
		  reset  : in  std_logic;
		  clk    : in  std_logic
		);
end lcd ;
 
architecture Behavioral of lcd is

-------------------------------------------------------------------------------
-- INTERNAL SIGNALS   ---------------------------------------------------------
-------------------------------------------------------------------------------

--Defines the type for states in the state machine
type state_type is (IDLE, READ_DATA_0, READ_DATA_1);
 
--Declare the signal with the corresponding state type.
signal current_state : state_type;
signal temp: std_logic_vector(3 downto 0); 

constant N: integer := 12;
type arr is array (0 to N)of STD_LOGIC_vector (3 downto 0);
constant datas : arr := (x"3", x"2",x"8", x"0",x"8",x"0",x"1",x"0",x"6",x"0",x"c",x"5",x"0");
 
begin
 
  lcd_rw <= '0';
 
	process (clk) 
	  begin    
	  if rising_edge(clk) then 
		if (reset='1') then  
			temp <= "0000";
		else
			temp <= temp + 1;
                           if (temp = 2000000) then
                              temp <= "0000";
                           end if;
		end if;
		 end if;
	end process; 
  
  process(clk)
  begin
    if rising_edge(clk) then
       if reset = '1' then	
	  Current_State <= IDLE; 
       else
	  case Current_State is 	
		when IDLE =>
 
		      if temp <= 1000000 then
			lcd_e <= '1';
			for j in 12 downto 0 loop
			      data(j) <= datas(j) (3 downto 0);
			end loop;
			Current_State    <= IDLE;
		      else
			Current_State    <= READ_DATA_0;
		      end if;
					
		when READ_DATA_0 =>
					
		      if (temp >1000000) and (temp <2000000) then
				lcd_e <= '0';
				Current_State    <= READ_DATA_0;
		      else
				Current_State    <= READ_DATA_1;
		      end if;
				
		when READ_DATA_1 =>				
					
		       if temp = 2000000 then
			Current_State    <= IDLE;
		       else
			Current_State    <= READ_DATA_1;						
		       end if;			

		end case;
	end if;
     end if;
  end process;
end behavioral;

--
--	Package File Template
--
--	Purpose: This package defines supplemental types, subtypes, 
--		 constants, and functions 
--
--   To use any of the example code shown below, uncomment the lines and modify as necessary
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package pkg_lcd is

type t_data_array is array (0 to 12) of std_logic_vector (3 downto 0);

end pkg_lcd;

package body pkg_lcd is


 
end pkg_lcd;

 

[phobos1]

Here is an verilog example. Hope it helps
**broken link removed**