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lcd interfacing in spartan 3E using vhdl

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p11

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Code: 
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:43:01 05/22/2015 
-- Design Name: 
-- Module Name:    lcd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd is
    Port ( lcd : out  STD_LOGIC_vector ( 7 downto 0);
          rs : out  STD_LOGIC;
           rw : out  STD_LOGIC;
			  enable: out std_logic);
end lcd;

architecture Behavioral of lcd is

begin


lcd ( 7 downto 4 ) <= "0010" after 10 ns ;-------- 4 bit interface-----------

lcd ( 3 downto 0) <= "1000" after 10 ns ;


enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;


lcd ( 7 downto 4 ) <= "0010" after 10 ns ;-------- 4 bit interface-----------

lcd ( 3 downto 0) <= "1000" after 10 ns ;


 enable <= '1' after 10 ns ;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;




lcd ( 7 downto 4 ) <= "0010" after 10 ns ;-------- 4 bit interface-----------

lcd ( 3 downto 0) <= "1000" after 10 ns ;


enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;

----------reset display--------------


lcd ( 7 downto 4 ) <= "0000" after 10 ns ;

lcd ( 3 downto 0) <= "0001" after 10 ns ;

enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;



lcd ( 7 downto 4 ) <= "0000" after 10 ns ;

lcd ( 3 downto 0) <= "0001" after 10 ns ;

enable <= '1' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;




lcd ( 7 downto 4 ) <= "0000" after 10 ns ;

lcd ( 3 downto 0) <= "0001" after 10 ns ;

enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;

-------------- display on------------------


lcd ( 7 downto 4 ) <= "0000" after 10 ns ;
lcd ( 3 downto 0) <= "1110" after 10 ns ;

enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;


lcd ( 7 downto 4 ) <= "0000" after 10 ns ;

lcd ( 3 downto 0) <= "1110" after 10 ns ;

enable <= '1' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;


lcd ( 7 downto 4 ) <= "0000" after 10 ns ;

lcd ( 3 downto 0) <= "1110" after 10 ns ;

enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;


------------------  bring cursor to the 1st position -------------



lcd ( 7 downto 4 ) <= "1000" after 10 ns ;

lcd ( 3 downto 0) <= "0000" after 10 ns ;

enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;



lcd ( 7 downto 4 ) <= "1000" after 10 ns ;

lcd ( 3 downto 0) <= "0000" after 10 ns ;

enable <= '1' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;




lcd ( 7 downto 4 ) <= "1000" after 10 ns ;

lcd ( 3 downto 0) <= "0000" after 10 ns ;

enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;
--------------------- data display---------------------


lcd ( 7 downto 4 ) <= "0101" after 10 ns ;--------displaying p-----------

lcd ( 3 downto 0) <= "0000" after 10 ns ;

enable <= '1' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;



lcd ( 7 downto 4 ) <= "0101" after 10 ns ;--------displaying p-----------

lcd ( 3 downto 0) <= "0000" after 10 ns ;

enable <= '0' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;



lcd ( 7 downto 4 ) <= "0101" after 10 ns ;--------displaying p-----------

lcd ( 3 downto 0) <= "0000" after 10 ns ;

enable <= '1' after 10 ns;

rw <= '0' after 10 ns;

rs <= '0' after 10 ns;

end Behavioral;



here i have tried to diiaplay p in the first location of the first row . i have run the program , there is no syntax error , but i cant understand is there any logical error specially involving delay ...plz let me know if there is any specific delay required between 2 statement executions . here for safety i have applied a delay of 10 ns after each instruction.
 

After statements have no use in synthesised designs. They are removed during compilation. They are only used for simulation.

I suggest you remove these afters and then re ruin the code through your simulation testbench to check for the correct operation.
 

Also, as I described to another poster earlier this week, you do not initialize the LCD anywhere. There is a specific initialization routine that must be run after powerup in order for the LCD to display anything at all. IIRC, that LCD is a common HD44780-based character display and you can find a link to it's init routine in the post I made a few days ago.


r.b.
 

if initializaton of lcd means entry mode set, display on display off , clear display , all this , then i have done it .. will u plz explain once more .
 

p11 said:
if initializaton of lcd means entry mode set, display on display off , clear display , all this , then i have done it .. will u plz explain once more .
Click to expand...

The problem is you've written your code as a "program" (like in software with delays).

In VHDL you write a description of hardware (i.e. a text description of the logic circuit).

That is why Tricky said to remove all the after statements, you'll find out that the simulation now just assigns the last assignment to a LHS signal and none of the previous assignments occur. If you want to do something based on time intervals you have to use a clock and a counter or a clock and FSM to sequence through the operations required.

You need to read a VHDL book or read a VHDL tutorial.
 

Well, the initialization sequence has long delays between steps, (i.e. 4.3 ms, 10us, etc) and I see nowhere in your code where you implement these long delays, which are required. Therefore I assumed you have not initialized it correctly.

I am assuming you are using a 16x2 character display.

r.b.
 

Code: 
---------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:43:01 05/22/2015 
-- Design Name: 
-- Module Name:    lcd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd is
    Port ( lcd : out  STD_LOGIC_vector ( 7 downto 0);
          rs : out  STD_LOGIC;
           rw : out  STD_LOGIC;
			  enable: out std_logic);
end lcd;

architecture Behavioral of lcd is

begin
process

begin



 lcd ( 7 downto 4 ) <= "0010"  ;-------- 4 bit interface-----------
			
			wait for 40 ms;

lcd ( 3 downto 0) <= "1000"  ;
wait for 40 ms;


enable <= '0' ;
wait for 1 ms;

rw <= '0' ;
wait for 1 ms;

rs <= '0' ;
wait for 1 ms;


lcd ( 7 downto 4 ) <= "0010"  ;-------- 4 bit interface-----------
wait for 40 ms;

lcd ( 3 downto 0) <= "1000" ;
wait for 40 ms;


 enable <= '1'  ;
wait for 1 ms;
rw <= '0' ;

wait for 1 ms;

rs <= '0' ;
wait for 1 ms;




lcd ( 7 downto 4 ) <= "0010"  ;-------- 4 bit interface-----------

wait for 40 ms;
lcd ( 3 downto 0) <= "1000"  ;

wait for 40 ms;


enable <= '0' ;

wait for 1 ms;
rw <= '0' ;
wait for 1 ms;

rs <= '0' ;
wait for 1 ms;

----------reset display--------------


lcd ( 7 downto 4 ) <= "0000"  ;
wait for 40 ms;

lcd ( 3 downto 0) <= "0001" ;
wait for 40 ms;

enable <= '0' ;
wait for 1 ms;

rw <= '0' ;
wait for 1 ms;

rs <= '0' ;
wait for 1  ms;



lcd ( 7 downto 4 ) <= "0000" ;
wait for 40 ms;

lcd ( 3 downto 0) <= "0001"  ;
wait for 1 ms;

enable <= '1' ;
wait for 1 ms;

rw <= '0' ;
wait for 1 ms;

rs <= '0' ;
wait for 1 ms;




lcd ( 7 downto 4 ) <= "0000" ;
wait for 1 ms;

lcd ( 3 downto 0) <= "0001" ;
wait for 1 ms;

enable <= '0' ;
wait for 1 ms;

rw <= '0' ;
wait for 1 ms;

rs <= '0' ;
wait for 1 ms;

-------------- display on------------------


lcd ( 7 downto 4 ) <= "0000"  ;
wait for 10 ns;
lcd ( 3 downto 0) <= "1110"  ;
wait for 10 ns;

enable <= '0' ;
wait for 10 ns;

rw <= '0' ;
wait for 10 ns;

rs <= '0' ;
wait for 10 ns;


lcd ( 7 downto 4 ) <= "0000"  ;

wait for 40 ms;
lcd ( 3 downto 0) <= "1110"  ;
wait for 40 ms;

enable <= '1' ;
wait for 1 ms;

rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;


lcd ( 7 downto 4 ) <= "0000" ;
wait for 40 ms;

lcd ( 3 downto 0) <= "1110" ;
wait for 40 ms;

enable <= '0' ;
wait for 1 ms;

rw <= '0' ;
wait for 1 ms;

rs <= '0';
wait for 1 ms;


------------------  bring cursor to the 1st position -------------



lcd ( 7 downto 4 ) <= "1000"  ;
wait for 40 ms;

lcd ( 3 downto 0) <= "0000" ;
wait for 40 ms;

enable <= '0';
wait for 1 ms;

rw <= '0';
wait for 1 ms;

rs <= '0';
wait for 1 ms;


lcd ( 7 downto 4 ) <= "1000"  ;
wait for 40 ms;

lcd ( 3 downto 0) <= "0000"  ;
wait for 40 ms;

enable <= '1' ;
wait for 1 ms;

rw <= '0' ;
wait for 1 ms;

rs <= '0' ;
wait for 1 ms;




lcd ( 7 downto 4 ) <= "1000"  ;

wait for 40 ms;
lcd ( 3 downto 0) <= "0000"  ;
wait for 40 ms;

enable <= '0';
wait for 1 ms;

rw <= '0' ;
wait for 1 ms;

rs <= '0' ;

wait for 1 ms;
--------------------- data display---------------------


lcd ( 7 downto 4 ) <= "0101"  ;--------displaying p-----------

wait for 40 ms;

lcd ( 3 downto 0) <= "0000"  ;

wait for 40 ms;

enable <= '1' ;
wait for 1 ms;

rw <= '0' ;

wait for 1 ms;

rs <= '0' ;
wait for 1 ms;



lcd ( 7 downto 4 ) <= "0101" ;--------displaying p-----------
wait for 40 ms;
lcd ( 3 downto 0) <= "0000" ;

wait for 40 ms;
enable <= '0';

wait for 1 ms;

rw <= '0' ;

wait for 1 ms;

rs <= '0' ;
wait for 1 ms;



lcd ( 7 downto 4 ) <= "0101"  ;--------displaying p-----------

    wait for 40 ms;

lcd ( 3 downto 0) <= "0000" ;

wait for 40 ms;

enable <= '1' ;

wait for 1 ms;


rw <= '0' ;

wait for 1  ms;

rs <= '0' ;

wait for 1 ms;

end process;

end Behavioral;



will it work now ?
 

will it work now ?
Click to expand...

No. For several reasons.

First , wait for is not synthesizeable. You have to create the delays yourself with a synchronous counter. The value you count to is the delay divided by the clock period.

Second, the link I gave to the the other poster is .

Look at the initialization flowchart for either 4-bit or 8-bit interfacing (you didn't specify). The first thing it asks you to do is wait 15ms or longer for the power supply to stabilize. Did you do that?

After waiting for power stabilization, the first value you have to write to the LCD , according to the manufacturer, is the value 0011 on lcd (7 downto 4). You write 0010. At that point, and after seeing you use "wait for" statements, I didn't have to read any farther to know you were not initializing it correctly.

Follow one of those flowcharts and use counters to provide your delays.

r.b.
 

why we cant use "wait ". then when to use wait/after and when not ?

- - - Updated - - -

Code: 
---------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:43:01 05/22/2015 
-- Design Name: 
-- Module Name:    lcd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd is
    Port ( lcd : out  STD_LOGIC_vector (3 downto 0);
          rs : out  STD_LOGIC;
           rw : out  STD_LOGIC;
			  enable: out std_logic);
end lcd;

architecture Behavioral of lcd is

begin
process

begin

delay for 100 ms

 lcd ( 3 downto 0 ) <= "0011"  ;--------special case of function set-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;





lcd ( 3 downto 0 ) <= "0011"  ;--------special case of function set-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;





lcd ( 3 downto 0 ) <= "0011"  ;--------special case of function set-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;







lcd ( 3 downto 0 ) <= "0010"  ;--------initial function set to change interface -----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;







lcd ( 3 downto 0 ) <= "0010"  ;------- function set-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;



lcd ( 3 downto 0 ) <= "1000"  ;--------function set-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;




lcd ( 3 downto 0 ) <= "0000"  ;--------display-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;


lcd ( 3 downto 0 ) <= "1000"  ;--------special case of function set-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;





lcd ( 3 downto 0 ) <= "0000"  ;-------display off-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;


lcd ( 3 downto 0 ) <= "1000"  ;--------display off-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;





lcd ( 3 downto 0 ) <= "0000"  ;--------clear display-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;

lcd ( 3 downto 0 ) <= "0001"  ;--------clear display-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;




lcd ( 3 downto 0 ) <= "0000"  ;--------entry mode set -----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;



lcd ( 3 downto 0 ) <= "0110"  ;--------entry mode set -----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;


lcd ( 3 downto 0 ) <= "0000"  ;-------display on-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;


lcd ( 3 downto 0 ) <= "1100"  ;--------display on-----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '0' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;




lcd ( 3 downto 0 ) <= "0101"  ;--------data display -----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '1' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;
end process;




lcd ( 3 downto 0 ) <= "0000"  ;-------- data display -----------
			delay  for 100 ms;
			
			
			
			enable <= '1' ;
delay for 100 ms;

       rw <= '0' ;
delay for 100 ms;

         rs <= '1' ;
delay for 100 ms;

          enable <= '0' ;
delay for 100 ms;

end Behavioral;


is it ok now... here delay for 100ms will be replaced by a counter for delay .. dont take it as a statement .
 

There is no such statement as "delay", there is only "wait" and wait is not suitable for synthesis - it is for modelling a circuit only.

Please, please please read a book on digital logic design and a VHDL tutorial.
 

i have written , that dont take delay as a statement , that will be replaced by a counter for delay . plz check my above post .i want to know that the rest process of initialization and data display in lcd is correct or not .
 

Even without the delays, the code does not describe a logic circuit. It is written as if vhdl is software. So it will not work

Have you drawn a circuit diagram?
 

will u plz explain me that what did you mean by" is written as if vhdl is software" by giving an example of a program written in both software language and then in vhdl, so that i can clearly understand my fault . plz help.
 

A peice of software is like your code - a long sequence of events
VHDL is NOT a programming language. It is a description language. You draw the circuit you want then describe it with VHDL

Please, go read a VHDL book and tutorial
 

Code: 
 ---------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:43:01 05/22/2015 
-- Design Name: 
-- Module Name:    lcd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd is
    Port ( data : out  STD_LOGIC_vector (3 downto 0);
          lcd_rs : out  STD_LOGIC;
           lcd_rw : out  STD_LOGIC;
			  lcd_e: out std_logic;
			  clk : in STD_LOGIC);
end lcd ;

architecture Behavioral of lcd is


constant N: integer := 13;

type arr is array (1 to n)of STD_LOGIC_vector (3 downto 0);

constant datas : arr := (x"3", x"2",x"8", x"0",x"8",x"0",x"1",x"0",x"6",x"0",x"c",x"5",x"0");

begin

lcd_rw <= '0';
process(clk)

variable i :integer :=0;
variable j :integer :=1;
  

begin

if (clk' event and clk ='1')  then

if i <= 1000000 then

i := i+1;
lcd_e <= '1';
data <= datas(j) (3 downto 0);


else if i >1000000 and i <2000000 then

i:= i+1;

lcd_e <= '0';

else if i = 2000000 then

j := j+1;
i:= 0;
end if;







if j <= 11 then 

lcd_rs <= '0';

else if j > 11 then 

lcd_rs <= '1';

end if;

if j =  13 then 
j :=11;
 end if;
 end if;
 
 end process;.......... line 100..........
 
    end behavioral;


ERROR:HDLParsers:164 - "C:/led/counter.vhd" Line 100. parse error, unexpected PROCESS, expecting IF
 

I suggest looking at state machines to do the various stages.
You can move to a state depending on a value in a counter.

Implement a strobe entity that pulses at ms, us, sec, minutes (whatever). Count on the strobe. Transition state at specified count values.
 

Properly formatted according to the way you wrote the if-else structures, resulting in incomplete if...end if constructs.
Code VHDL - [expand]
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if (clk'event and clk ='1')  then
    if i <= 1000000 then
      i := i+1;
      lcd_e <= '1';
      data <= datas(j) (3 downto 0);
    else
      if i >1000000 and i <2000000 then
        i:= i+1;
        lcd_e <= '0';
      else
        if i = 2000000 then
          j := j+1;
          i:= 0;
        end if;
 
        if j <= 11 then 
          lcd_rs <= '0';
        else
          if j > 11 then 
            lcd_rs <= '1';
          end if;
 
          if j =  13 then 
            j :=11;
          end if;
        end if;


But I'm pretty sure you meant to write:
Code VHDL - [expand]
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if (clk'event and clk ='1')  then
    if i <= 1000000 then
      i := i+1;
      lcd_e <= '1';
      data <= datas(j) (3 downto 0);
    elsif i >1000000 and i <2000000 then
      i:= i+1;
      lcd_e <= '0';
    elsif i = 2000000 then
      j := j+1;
      i:= 0;
    end if;
 
    if j <= 11 then 
      lcd_rs <= '0';
    elsif j > 11 then 
      lcd_rs <= '1';
    end if;
 
    if j =  13 then 
      j :=11;
    end if;
  end if;

Note that the syntax is elsif and not else if. The statements else if mean something completely different as you can see in the first code sample.
 
  • Like
Reactions: p11

    P

    p11

    Points: 2
    Helpful Answer Positive Rating
ok, then what does "else if " mean in vhdl?
 

it means...
Code VHDL - [expand]
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if (a = b) then
else -- a /= b       \ else if
  if (c = d) then -- /
  end if;
end if;


of course this example is simple so it would be the same as:
Code VHDL - [expand]
1
2
3

if (a = b) then
elsif (c = d) then
end if;
 

Code: 
---------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:43:01 05/22/2015 
-- Design Name: 
-- Module Name:    lcd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd is
    Port ( data : out  STD_LOGIC_vector (3 downto 0);
          lcd_rs : out  STD_LOGIC;
           lcd_rw : out  STD_LOGIC;
			  lcd_e: out std_logic;
			  clLk : in STD_LOGIC);
end lcd ;

architecture Behavioral of lcd is


constant N: integer := 13;

type arr is array (1 to n)of STD_LOGIC_vector (3 downto 0);

constant datas : arr := (x"3", x"2",x"8", x"0",x"8",x"0",x"1",x"0",x"6",x"0",x"c",x"5",x"0");

begin

lcd_rw <= '0';
process(clLk)

variable i :integer :=0;
variable j :integer :=1;
  

begin

if clLk ='1'  then

if i <= 1000000 then

i := i+1;
lcd_e <= '1';
data <= datas(j) (3 downto 0);


elsif i >1000000 and i <2000000 then

i:= i+1;

lcd_e <= '0';

elsif i = 2000000 then

j := j+1;
i:= 0;
end if;







if j <= 11 then 

lcd_rs <= '0';

elsif j > 11 then 

lcd_rs <= '1';

end if;

if j =  13 then 
j :=11;
 end if;
 end if;
 
 end process;
    end behavioral;




WARNING:Xst:737 - Found 32-bit latch for signal <i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <j>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <lcd_e>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <data>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <lcd_rs>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.





plz give me an idea about these warnings , because implementation of the design is getting failed .........:sad::sad::sad::sad::sad::sad:


well this a code for lcd , to diplay p . i have used spartan 3e fpga board , and ise 14.1 vhdl.
 

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