----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:43:01 05/22/2015
-- Design Name:
-- Module Name: lcd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd is
Port ( lcd : out STD_LOGIC_vector ( 7 downto 0);
rs : out STD_LOGIC;
rw : out STD_LOGIC;
enable: out std_logic);
end lcd;
architecture Behavioral of lcd is
begin
lcd ( 7 downto 4 ) <= "0010" after 10 ns ;-------- 4 bit interface-----------
lcd ( 3 downto 0) <= "1000" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "0010" after 10 ns ;-------- 4 bit interface-----------
lcd ( 3 downto 0) <= "1000" after 10 ns ;
enable <= '1' after 10 ns ;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "0010" after 10 ns ;-------- 4 bit interface-----------
lcd ( 3 downto 0) <= "1000" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
----------reset display--------------
lcd ( 7 downto 4 ) <= "0000" after 10 ns ;
lcd ( 3 downto 0) <= "0001" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "0000" after 10 ns ;
lcd ( 3 downto 0) <= "0001" after 10 ns ;
enable <= '1' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "0000" after 10 ns ;
lcd ( 3 downto 0) <= "0001" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
-------------- display on------------------
lcd ( 7 downto 4 ) <= "0000" after 10 ns ;
lcd ( 3 downto 0) <= "1110" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "0000" after 10 ns ;
lcd ( 3 downto 0) <= "1110" after 10 ns ;
enable <= '1' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "0000" after 10 ns ;
lcd ( 3 downto 0) <= "1110" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
------------------ bring cursor to the 1st position -------------
lcd ( 7 downto 4 ) <= "1000" after 10 ns ;
lcd ( 3 downto 0) <= "0000" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "1000" after 10 ns ;
lcd ( 3 downto 0) <= "0000" after 10 ns ;
enable <= '1' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "1000" after 10 ns ;
lcd ( 3 downto 0) <= "0000" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
--------------------- data display---------------------
lcd ( 7 downto 4 ) <= "0101" after 10 ns ;--------displaying p-----------
lcd ( 3 downto 0) <= "0000" after 10 ns ;
enable <= '1' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "0101" after 10 ns ;--------displaying p-----------
lcd ( 3 downto 0) <= "0000" after 10 ns ;
enable <= '0' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
lcd ( 7 downto 4 ) <= "0101" after 10 ns ;--------displaying p-----------
lcd ( 3 downto 0) <= "0000" after 10 ns ;
enable <= '1' after 10 ns;
rw <= '0' after 10 ns;
rs <= '0' after 10 ns;
end Behavioral;
if initializaton of lcd means entry mode set, display on display off , clear display , all this , then i have done it .. will u plz explain once more .
---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:43:01 05/22/2015
-- Design Name:
-- Module Name: lcd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd is
Port ( lcd : out STD_LOGIC_vector ( 7 downto 0);
rs : out STD_LOGIC;
rw : out STD_LOGIC;
enable: out std_logic);
end lcd;
architecture Behavioral of lcd is
begin
process
begin
lcd ( 7 downto 4 ) <= "0010" ;-------- 4 bit interface-----------
wait for 40 ms;
lcd ( 3 downto 0) <= "1000" ;
wait for 40 ms;
enable <= '0' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
lcd ( 7 downto 4 ) <= "0010" ;-------- 4 bit interface-----------
wait for 40 ms;
lcd ( 3 downto 0) <= "1000" ;
wait for 40 ms;
enable <= '1' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
lcd ( 7 downto 4 ) <= "0010" ;-------- 4 bit interface-----------
wait for 40 ms;
lcd ( 3 downto 0) <= "1000" ;
wait for 40 ms;
enable <= '0' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
----------reset display--------------
lcd ( 7 downto 4 ) <= "0000" ;
wait for 40 ms;
lcd ( 3 downto 0) <= "0001" ;
wait for 40 ms;
enable <= '0' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
lcd ( 7 downto 4 ) <= "0000" ;
wait for 40 ms;
lcd ( 3 downto 0) <= "0001" ;
wait for 1 ms;
enable <= '1' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
lcd ( 7 downto 4 ) <= "0000" ;
wait for 1 ms;
lcd ( 3 downto 0) <= "0001" ;
wait for 1 ms;
enable <= '0' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
-------------- display on------------------
lcd ( 7 downto 4 ) <= "0000" ;
wait for 10 ns;
lcd ( 3 downto 0) <= "1110" ;
wait for 10 ns;
enable <= '0' ;
wait for 10 ns;
rw <= '0' ;
wait for 10 ns;
rs <= '0' ;
wait for 10 ns;
lcd ( 7 downto 4 ) <= "0000" ;
wait for 40 ms;
lcd ( 3 downto 0) <= "1110" ;
wait for 40 ms;
enable <= '1' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
lcd ( 7 downto 4 ) <= "0000" ;
wait for 40 ms;
lcd ( 3 downto 0) <= "1110" ;
wait for 40 ms;
enable <= '0' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0';
wait for 1 ms;
------------------ bring cursor to the 1st position -------------
lcd ( 7 downto 4 ) <= "1000" ;
wait for 40 ms;
lcd ( 3 downto 0) <= "0000" ;
wait for 40 ms;
enable <= '0';
wait for 1 ms;
rw <= '0';
wait for 1 ms;
rs <= '0';
wait for 1 ms;
lcd ( 7 downto 4 ) <= "1000" ;
wait for 40 ms;
lcd ( 3 downto 0) <= "0000" ;
wait for 40 ms;
enable <= '1' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
lcd ( 7 downto 4 ) <= "1000" ;
wait for 40 ms;
lcd ( 3 downto 0) <= "0000" ;
wait for 40 ms;
enable <= '0';
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
--------------------- data display---------------------
lcd ( 7 downto 4 ) <= "0101" ;--------displaying p-----------
wait for 40 ms;
lcd ( 3 downto 0) <= "0000" ;
wait for 40 ms;
enable <= '1' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
lcd ( 7 downto 4 ) <= "0101" ;--------displaying p-----------
wait for 40 ms;
lcd ( 3 downto 0) <= "0000" ;
wait for 40 ms;
enable <= '0';
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
lcd ( 7 downto 4 ) <= "0101" ;--------displaying p-----------
wait for 40 ms;
lcd ( 3 downto 0) <= "0000" ;
wait for 40 ms;
enable <= '1' ;
wait for 1 ms;
rw <= '0' ;
wait for 1 ms;
rs <= '0' ;
wait for 1 ms;
end process;
end Behavioral;
will it work now ?
---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:43:01 05/22/2015
-- Design Name:
-- Module Name: lcd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd is
Port ( lcd : out STD_LOGIC_vector (3 downto 0);
rs : out STD_LOGIC;
rw : out STD_LOGIC;
enable: out std_logic);
end lcd;
architecture Behavioral of lcd is
begin
process
begin
delay for 100 ms
lcd ( 3 downto 0 ) <= "0011" ;--------special case of function set-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0011" ;--------special case of function set-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0011" ;--------special case of function set-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0010" ;--------initial function set to change interface -----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0010" ;------- function set-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "1000" ;--------function set-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0000" ;--------display-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "1000" ;--------special case of function set-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0000" ;-------display off-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "1000" ;--------display off-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0000" ;--------clear display-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0001" ;--------clear display-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0000" ;--------entry mode set -----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0110" ;--------entry mode set -----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0000" ;-------display on-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "1100" ;--------display on-----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '0' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
lcd ( 3 downto 0 ) <= "0101" ;--------data display -----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '1' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
end process;
lcd ( 3 downto 0 ) <= "0000" ;-------- data display -----------
delay for 100 ms;
enable <= '1' ;
delay for 100 ms;
rw <= '0' ;
delay for 100 ms;
rs <= '1' ;
delay for 100 ms;
enable <= '0' ;
delay for 100 ms;
end Behavioral;
---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:43:01 05/22/2015
-- Design Name:
-- Module Name: lcd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd is
Port ( data : out STD_LOGIC_vector (3 downto 0);
lcd_rs : out STD_LOGIC;
lcd_rw : out STD_LOGIC;
lcd_e: out std_logic;
clk : in STD_LOGIC);
end lcd ;
architecture Behavioral of lcd is
constant N: integer := 13;
type arr is array (1 to n)of STD_LOGIC_vector (3 downto 0);
constant datas : arr := (x"3", x"2",x"8", x"0",x"8",x"0",x"1",x"0",x"6",x"0",x"c",x"5",x"0");
begin
lcd_rw <= '0';
process(clk)
variable i :integer :=0;
variable j :integer :=1;
begin
if (clk' event and clk ='1') then
if i <= 1000000 then
i := i+1;
lcd_e <= '1';
data <= datas(j) (3 downto 0);
else if i >1000000 and i <2000000 then
i:= i+1;
lcd_e <= '0';
else if i = 2000000 then
j := j+1;
i:= 0;
end if;
if j <= 11 then
lcd_rs <= '0';
else if j > 11 then
lcd_rs <= '1';
end if;
if j = 13 then
j :=11;
end if;
end if;
end process;.......... line 100..........
end behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 if (clk'event and clk ='1') then if i <= 1000000 then i := i+1; lcd_e <= '1'; data <= datas(j) (3 downto 0); else if i >1000000 and i <2000000 then i:= i+1; lcd_e <= '0'; else if i = 2000000 then j := j+1; i:= 0; end if; if j <= 11 then lcd_rs <= '0'; else if j > 11 then lcd_rs <= '1'; end if; if j = 13 then j :=11; end if; end if;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 if (clk'event and clk ='1') then if i <= 1000000 then i := i+1; lcd_e <= '1'; data <= datas(j) (3 downto 0); elsif i >1000000 and i <2000000 then i:= i+1; lcd_e <= '0'; elsif i = 2000000 then j := j+1; i:= 0; end if; if j <= 11 then lcd_rs <= '0'; elsif j > 11 then lcd_rs <= '1'; end if; if j = 13 then j :=11; end if; end if;
Code VHDL - [expand] 1 2 3 4 5 if (a = b) then else -- a /= b \ else if if (c = d) then -- / end if; end if;
Code VHDL - [expand] 1 2 3 if (a = b) then elsif (c = d) then end if;
---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:43:01 05/22/2015
-- Design Name:
-- Module Name: lcd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd is
Port ( data : out STD_LOGIC_vector (3 downto 0);
lcd_rs : out STD_LOGIC;
lcd_rw : out STD_LOGIC;
lcd_e: out std_logic;
clLk : in STD_LOGIC);
end lcd ;
architecture Behavioral of lcd is
constant N: integer := 13;
type arr is array (1 to n)of STD_LOGIC_vector (3 downto 0);
constant datas : arr := (x"3", x"2",x"8", x"0",x"8",x"0",x"1",x"0",x"6",x"0",x"c",x"5",x"0");
begin
lcd_rw <= '0';
process(clLk)
variable i :integer :=0;
variable j :integer :=1;
begin
if clLk ='1' then
if i <= 1000000 then
i := i+1;
lcd_e <= '1';
data <= datas(j) (3 downto 0);
elsif i >1000000 and i <2000000 then
i:= i+1;
lcd_e <= '0';
elsif i = 2000000 then
j := j+1;
i:= 0;
end if;
if j <= 11 then
lcd_rs <= '0';
elsif j > 11 then
lcd_rs <= '1';
end if;
if j = 13 then
j :=11;
end if;
end if;
end process;
end behavioral;
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