Of course it is and not only these features. The question is, whether you have an access to proper tools and/or licenses.
Using Virtuoso Layout XL/GXL there is a direct binding between nets and devices in schematic and layout, so tool showing in real time which connection are done properly, which are broken and where the shorts exists. Virtuoso Layout EAD/EXL allows real time extraction of current state of layout with EM/IR checks. Moreover, it allows to generates netlists for parasitic aware design flow to reduce number of desing steps/iterations.
I am pretty sure you have an access to Virtuoso Layout XL license, so the only thing you need to do is to read tool documentation (is in your cadence_IC_installation/doc/VXL/).
Dear Dominik
Thank you for your suggestion,
Actually I have access to the Virtuoso Layout XL, I used before the property of monitoring the connection in real time, this procedure will work fine if I bring the transistor as it from the schematic, but as long as I divide it for matching it will become messy.
I never worked with EAD but I will try to search on it.
In short and as I understood from you, from the Layout XL I can check about the LVS without running the LVS, but by the option of real time monitoring the connections provided by XL environment.
To extract the parasitics at any partial level of the layout design.
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I like to build my layouts hierarchically, and DRC / LVS along
the way. So what if the cell is used only once and never
again?
Dear freebird,
can you please tell me how to build the layouts hierarchically, I do it by splitting the circuit in to many symbols but as I said from my first post this procedure is also consuming time because then I have to connect these symbols. I was thinking to make the layouts hierarchically by layout some transistors in the same circuit but the LVS then start to complain about the non-layout transistors.
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Let me please take this simple folded OTA as an example to make the answer more clear on how to build the circuit part by part hierarchically and checking the LVS continuously.
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in the image below I am showing you how I am dividing the circuit in to individual symbols, where every symbol is represented by the rectangular