Hi guys and thanks for the reply.
@scolis_GT
The layout that I am doing is from a 3-current mirror OTA. It is designed alone, in a separated schematic from the rest of the blocks - more, all the blocks were separated, that is, I did sub-blocks and in the end I have put them together. To do the layout I use each separated block (sub-block).
So this layout is being made apart from the rest of the other block.
However, what are you suggesting is to do only the layout of the differential pair, alone two transistors with the pins?
I notice that scolis_GT, that cadence puts the D and S. When I flipped the transistor horizontally, the D and S flipped too.
For the diff pair, the N-well is the same net so it should not give you any warnings/errors unless it is a DRC error.
It is a curious thing. This because, as you can see from the picture, when I just put together each transistor by the limit NWELL layer nothing happens. However, when I join the D with D and S with S, automatically cadence yellow box warning pops up.
@dick_freebird
It happens in the past, while in school, do the layout in that way. I done the layout by clicking on generate all from source.
Now, I am doing differently. I am picking each transistor from the schematic and put him in the layout separatly. I picked, for example, with the option: generate selected from the source (I think it is not the auto mode) the differential pair transistors and did the layout. Then the load from the differential pair, etc.
Any ideas? Maybe posting in cadence forum?
Regards.