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Layout issue with Digital STD Cell in cadence Virtuoso

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Junior Member level 3
Jul 20, 2005
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Hi everyone. I have designed a small digital block with verilog.

Then I did the synthesis with synopsis DC.

After that I generated the layout in Cadence SoC encounter with the STD cell lib provided by the foundry.

Next I export the encounter layout into a GDS file. I want to import my GDS into cadence virtuoso layout editor to check DRC and LVS. Later I will combine the digital layout with my analog layout.

I have some problems when import my GDS file into cadence virtuoso.

Below are the two screen shots i captured.

The firsts one is the layout in cadence SoC Encounter. The 2nd one is the thing I got after importing my GDS into cadence virtuoso. I basically got nothing. there is no metal layers...

Can anyone help me with this.??

I did first import my STD cell GDS into the cadence virtuoso. After that I important my GDS file. But it is not correct.

Please help..... Im desperate now...

You'll need to attach tech file to the library where your imported design will go to.

Hey ebuddy, thanks for the help.

do you mean the tech file of the PDK i am using??

where can I find this tech file??

Yes, the tech file is the one that comes with PDK. When you create a new library in icfb, it asks you if you want to attach an existing tech file, say yes and pick the proper tech file. Then import GDS, you shall see the right result.

If you have not installed PDK yet, do it first. You probably need help from your CAD group.

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