1) You should be able to stream in the pad, extract the layout,
turn it into an analog_extracted view and make a corresponding
symbol, then set up a Spectre simulation and get whatever you
want from it. But there might be enough info in TSMC library
docs to skip all of that - don't they publish pad cell attributes
like min drive strength (perhaps as VOL@ILOAD) or maybe even
an IBIS model?
Ability to drive a (capacitive, as most are) load really depends
on frequency. I wouldn't go past 50MHz on a single ended CMOS
driver myself. But you don't say -what- circuit is under pad -
maybe it isn't even logic but some weak sauce analog signal
that will get its lunch money stolen by just the hum from
fluorescent lights. There's worse things than shunt C to Gnd,
and plenty of them. Maybe you should work backward from
the real world and what the ADC says its driver needs to
look like - some, especially high speed differential, seem to
have gotten pretty demanding about what you have to
feed them with, for part specs to apply.
2) This sounds wrong, or you've misused globals or some
other mis-design. You can route power as a signal or you
can use named! nets / global symbols (you should have
at least half a dozen not counting the gnd{}! ones). The
JI technology will need you to put the most negative
supply to the substrate and you may have the misfortune
to find that some library developer has made bad choices
for you, or required you to override things like the symbol
property for NMOS body connection. I have done many
multirail chips with no such problems.
3) Yes, density rules are stupidly demanding and all for the
fab rats' convenience. Anywhere you might care about the
local capacitance and couplings changing post-review, you
ought to place fills yourself. I liked to make my own fills as
plate capacitors, which at least are useful as decoupling.
In the end you will have to act humble and request waivers
once you have done your best.