Layout from Verilog code

[Eminent.Engineer]

Hi
I have designed my system in Verilog HDL now I want to design Layout of the complete system using CADENCE tool from verilog code, so kindly mention the steps involved.
if any related reading material is available then kindly post the links that will be really helpful.

Thanks to all.

 

[sudheerkm]

use soc encounter

if u have std cell libraries

just google it

will get lot of materials