Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Layout from Verilog code

Status
Not open for further replies.

Eminent.Engineer

Member level 3
Member level 3
Joined
Oct 8, 2012
Messages
54
Helped
10
Reputation
20
Reaction score
10
Trophy points
1,288
Activity points
1,630
Hi
I have designed my system in Verilog HDL now I want to design Layout of the complete system using CADENCE tool from verilog code, so kindly mention the steps involved.
if any related reading material is available then kindly post the links that will be really helpful.

Thanks to all.
 

use soc encounter

if u have std cell libraries

just google it

will get lot of materials
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top