Layout Error in GND and Vss

[Laurenz88]

Hello Professionals,

in my design, i have ground, Vdda, and Vss supllies, and i find hard to clean up the LVS errors since gnd and vss are being read as one in cdesigner and are considered shorted since in my opamp the nmos' bulk and sources are conncted to the negative supply vss and the nmos' bulk and sources of my transmission gate is connected to ground...i made the same guard ring for both with different names of pin but still error occured and is considered shorted by the cdesigner.. I find it hard to layout this specifications....
Can somebody please tell me how to solve this kind of problem....

THANK you....

 

[steinar96]

If GND and VSS are regarded as the same in the program you should rename one network since GND and VSS are nothing more then network names.

 

[Laurenz88]

If GND and VSS are regarded as the same in the program you should rename one network since GND and VSS are nothing more then network names.

my problem is how to layout the guard ring for an nmos which is the source and and its bulk is connected to the negative supply vss= -1.65. An error occurred when i try to check the LVS and it is the gnd and the vss... I have made the same guard ring for both nmos with diff,metal1,contacts and an implant PIMP and i also put different pin names namely gnd for the nmos conncted to ground and vss for nmos connected to vss.. but still same error occurred....

Please help...

 

[dgnani]

A p-implanted diffusion ring will not isolate an NFET body from other NFET bodies, they will still be soft-connected. The only way to have NFET's with different body voltage is to use deep n-well to create an isolated p-well region

 

[Teddy]

In case you do not want to short them (ie GND=0V and VSS=-1.65V) you will have to use devices in deep Nwell - which is 5 terminal device. In that case you have to change both schematic and layout.

 

[dgnani]

In case you do not want to short them (ie GND=0V and VSS=-1.65V) you will have to use devices in deep Nwell - which is 5 terminal device. In that case you have to change both schematic and layout.

A deep-nwell NFET is usually a 6-terminal device: you add isolation well bias and global substrate

 

[starinspace]

There is no need to use five terminal devices. In the normal layout which u have done now, either isolate the transistors connected to ground using deep nwell or vice versa. This will create an isolated p-substrate within that n-well which whose potential can be different than your die p-substrate potential. By placing transistors in different Deep nwells u can give them different body potentials.

 

[dgnani]

hi starinspace
depending on how dnw nfets are extracted by your LVS/RCX rules you might be forced to use 5-6 terminal devices or not; even if your rules are forgiving in that sense, it is a bad idea not to use them because in case of LVS violations the results will be either very confusing or completely ignore softconnect violations...
By the way before you reply to a thread it is a good idea to check its date...

There is no need to use five terminal devices. In the normal layout which u have done now, either isolate the transistors connected to ground using deep nwell or vice versa. This will create an isolated p-substrate within that n-well which whose potential can be different than your die p-substrate potential. By placing transistors in different Deep nwells u can give them different body potentials.