Layout considerations for this full-bridge SMPS

[diegocip]

Hi,

I'm with a doubt with this SMPS full-bridge PCB, also with the rectifier PCB too.

Note: Because of size and dissipation, rectifier, full-bridge, transformer, and secondary rectifier are at separated PCBs (I know, stray inductance between the PCBs, but they will be shorter and twisted wires, calculations shows a very small stray inductance).

So the PCB of the full-bridge:

The question is, does the tracks of the legs that runs under the IGBTs packages cause any problem?

To have a get a better understanding:

If so, moving it the the other side will help?
like this:

The same for the secondary rectifier diodes:

About the SMPS:

• DC Link voltage: ~340V.
• PEAK current at the IGBT: 75A (at full load on the peak of the switching waveform).
• Rectified secondary voltage: maximum of 25V/200A at full-load, and 60V at "no-load".
• Switching frequency: ~20Khz maybe a bit more if the switching becomes so audible.

---

Notes:

This is not the final design so it does not include snubbering nor gate drive. Also the edges of the traces will be rounded.

The DC BUS tracks although not easy to see is one on each side, so to reduce inductance and add capacitance, also giving a nice design and space use, based on https://xellers.wordpress.com/2013/03/14/general-purpose-h-bridge-inverter/.

Thanks in advance for your help.

 

[KlausST]

Hi,

your design is not bad.

The tracks under the isolated IGBT make no problem, as far as i can see. Leave it on the side of the IGBTs (see below)

Not necessary but you can improve:
* for the most top picture:
I hope i am right with this: top layer is blue. and it carries the +Supply. Bottom layer is red and it carries the -Supply=GND.
Then i´d fill the bottom layer with GND as much as possible.
Additionally i´d put a ceramic capacitor (size 1210) directely from highside_IGBT_collector to GND plane. This improves HF behaviour.
Place the drivers next to the IGBTs and be careful laying out the driver control lines.

For the secondary rectifier i see problems with the 250A. 1Oz of copper is definitely not sufficient. You must go for thicker plating.

Hope this helps

Klaus

added: just to give you an magnitude of power dissipation: With a 1 Oz copper i´d expect about 100W of power dissipation in the PCB.
so if you want a mx dissipation of 10W then you need a 10 Oz copper plating. BTW. skin effect is not significant.

 

[diegocip]

Thanks for your answer. Just affirm again, the base design of the full-bridge is from the link at the final of the article.

Leave it on the side of the IGBTs

My concern is that the two tracks have no ground plane and with that dv/dt and di/dt at the package this can cause some "strange" problems like the gate charging. Thanks for your explanation.

I hope i am right with this: top layer is blue. and it carries the +Supply. Bottom layer is red and it carries the -Supply=GND.

The fact I do not ground fill the other side, is to put some of circuit near the IGBTs, that is:
RCD/RC snubber, zener diodes to clamp any high potential on the gate of the IGBTs, and the drive circuit.

Place the drivers next to the IGBTs and be careful laying out the driver control lines.

The drive is by floating supplies and opto-isolators (TLP250), so basically the drive components at the place are a decoupling capacitor, the gate resistor, and maybe a diode.
(There's negative bias at the gate to improve immunity).

I searched and studied a good time a solution with transformer gate drive, as the maximum duty cycle is theoretical 0.5 max, it seems easy, but cross-conduction factor during off-time is one of the major problems.

For the secondary rectifier i see problems with the 250A. 1Oz of copper is definitely not sufficient. You must go for thicker plating.

Thanks, I plan to tin fill these high current traces to have a large cross-section area / less resistance.

 

[D.A.(Tony)Stewart]

I see a lot of problems with this design from dI/dt coupling, conductive losses on traces, no short circuit :sad: withstanding p rotection, no high voltage(3kV isolation from arcing.

Start over using busbars with common mode paths on opposite sides of insuator yet high voltage insulation with 1kA surge capability.

 

[KlausST]

Hi,

dI/dt coupling: I don´t see this critical. because the relativ large distance.

dU/dt coupling: Yes, with the IGBTs lying on the traces you get increased C_out, I expect it in the range of 10 pF. What C_Out do the IGBTs have?


drivers near gate: best is you do your design, then take a colored marker and show where the current flows to 1) charge and 2) discharge the gate.
here the drivers have large dU/dt and relatively large dI/dt.


For the secondary side you will need busbars as SunnySkyguy reccomended.


Klaus

 

[diegocip]

I see a lot of problems with this design from dI/dt coupling, conductive losses on traces, no short circuit :sad: withstanding p rotection, no high voltage(3kV isolation from arcing.

Start over using busbars with common mode paths on opposite sides of insuator yet high voltage insulation with 1kA surge capability.

Well the clearance respects and pass the 1.6Kv/mm UL functional isolation recommendation, that goes to 30Khz.

Why 3kV isolation from arcing? :shock: The bus should be at maximum 240VAC so ~340VAC, can go to 400 or 500V during turn-off of the switching cycle, even that, this is below the 1.6Kv clearance. Can you give-me more details please?

I remember this is only the full-bridge and the secondary rectifier (25VCC rectified at full load).
The control board, primary rectifier and capacitors, are not show.

Thank you.

 

[diegocip]

dU/dt coupling: Yes, with the IGBTs lying on the traces you get increased C_out, I expect it in the range of 10 pF. What C_Out do the IGBTs have?

Can you be more specific naming this capacitance C_out? sorry.

drivers near gate: best is you do your design, then take a colored marker and show where the current flows to 1) charge and 2) discharge the gate.
here the drivers have large dU/dt and relatively large dI/dt.

The drivers are floating-supplies (one for each IGBT) and a opto-coupler MOSFETs/IGBTs driver (TLP250) (1.5A peak). If is to know the current-loop of the drive, its from the floating supply some 10's cm away, to opto-coupler, resistor and direct to gate, then emitter and back to the floating-supply. That's why I chose floating supplies and opto-couplers, apart from the noise immunity, no latch at negative transients, negative bias to improve immunity and prevent conduction by miller effect, and so on.

Sure I can use bus-bars, thanks for the recommendation. But you really think its best, than using a large and tin filled PCB track (that should get near the cross-section of a bus-bar I have easy access? So, the idea is soldering the TO-247AC leads direct to the bus-bar?

Thanks

 

[KlausST]

Hi,

C_out = output capacitance of igbt (Gate to collector)

Driver: the most important is the path where the charge/discharge current of the gate goes. Some 10s cm is too long.
It is not important whether floating or not. The current is the same.

Klaus

 

[diegocip]

Hi,

C_out = output capacitance of igbt (Gate to collector)

Driver: the most important is the path where the charge/discharge current of the gate goes. Some 10s cm is too long.
It is not important whether floating or not. The current is the same.

Klaus

Hi,

The output capacitance of the IGBT is 245pF.
If the tracks will increase the capacitance too much, that's a good subject to moving it away, no?

Anyway, "output capacitance" seems to be "emitter to gate", and "gate to emitter" capacitances summed.
The Cres (collector to gate), as I know one of the most responsible for the Miller effect (charging of the gate by high di/dt) is 90pF.

Most of floating supply designers, commercial ones have near this distance from supply to drive IC. Again can you explain what is the concern?
There's a decoupling cap at the driver IC, so the current path will be mostly at it during peak gate charge. As the driver IC is located just next to the IGBT this should be a very small current loop.

Thanks again.

 

[diegocip]

Well, and this:



The clearance between pads are ~1.5mm (~2.4KV isolation) and between tracks and track to pin ~2.0mm (3.2KV isolation). (Values for a functional isolation of 1.6KV/mm).

To unique difficultly is making the two "tracks", it should be with a large gage wire (I think sink effect at that length does not imply so much resistance, anyway I could use litz wire), or using a small simple face PCB on top.

I really don't decided what is better by the trade offs of difficult soldering and mounting or the tracks behind the package.