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Full Bridge SMPS needs gate drive transformers for top and bottom FETs

cupoftea

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Hi,
Nobody ever does anything in SMPS if it means more cost and circuitry for no reason.

So why does everyone use gate drive transformer for top and bottom fets in a Full Bridge?....after all, surely you can get away without bothering for the bottom fets?

This is why, if you design a full bridge SMPS, for 400vdc input, and a 100W or more, then you must drive top and bottom fets with a gate drive transformer. Avoid the temptation of just using the raw fet drive to drive the bottom fets…even though it costs less…..you can see from reverse engineering them, that this is always done.

If you do not do it, then you risk reverse recovery of the upper fets anti-parallel diode, and lots of smoke. The fact is, that, if you just use the raw fet drive for the bottom fet, then it will turn on quicker, ..will then drag a spike of current through the upper fets CDS capacitance…..then there will be a resonant ring with the primary and the lower FETs cds, and the “back-swing” will go right through the upper anti-parallel diode….the top fet then turns on, so its (conducting) diode does not then get properly reverse recovered……and then when the bottom fet eventually turns on…yes , you’ve guessed it, the top diode is still conductive and a massive reverse recovery current spike goes through the bottom fet…..lets out the magic smoke.

This is why we see everyone doing this (driving both top and bottom fets with a gate drive transformer…even though it looks like you could leave it out for the bottom fet.)

Have you encountered this issue?...and have you got into using SiC FETs to get round it (internal diode has no reverse recovery).

And also, we can forget trying to simulate the issue...the sims dont model reverse recovery well enough.
 
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If you want to control dead time across, especially, the driver
line and temp then you want to match high and low side in
as many details as you can.

When I did my GaN driver HB design (long ago, now EOL) I
made the low side use the same bootstrap diode and internal
LDO, as the high side along with delay-matching the level
shifter with equal elements in the low side. Did I have to?
No, unless consistency of dead time across all, is a care-about.
Which given wanting to operate up to 30MHz, yeah, it gets
to be.
 
Thanks, ayk, GaN fortunately doesnt have the internal reverse recovering diode.....i pray they get cheaper , quicker!

Worse still is that Si FETs on digikey etc dont allow you to search them based on trr of the internal diode.

Adding an small inductor in the bridge can help a little in reducing the current spike that back-swings into the upper fets anti-parallel diode...as follows..
(thread 408664 on edaboard)..


Infineon coolMOS fets have low-ish trr
..but dont come in DPAK unfortunately
--- Updated ---

Anyone know of any low trr FETs rated 600V+?
 
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Thanks Tony, the TP65H is great, and just £1.20, but not in stock anywhere...still...that would provide an answer to this problem.

TP44400 looks good too....just find out how to drive it on...

TP44400

Does anyone know how to drive the TP44400?...datasheet is one page long and just says "5V or 12v"...what does that mean?.....what is abs max? What is the gate capacitance?...what is VGsth?
--- Updated ---

This one is more explanatory....but the 1.2v vgsth will be a problem with gate drive transformer/series cap ring after sudden duty cycle change. (spurious on driving)
--- Updated ---

..mind you with Qgtot of 2nC, maybe we can damp the heck out of the gate drive and still drive the GaN on quick......5V zener at the gate to protect.....in fact , woudl need hi side fet driver with supply clamped at 5v, to be cerain it nebver got 7V+
 
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