If you make layout as small as possible (of course meeting DRC rules) the connection lines are shorter. So it seems that paracitic capacitors are decreased. But at the other hand the separatrion between metal paths is also smaller so the parasitic capacitance can even increase. So, one should decrease metal lines length and keep separation in reasonable value. Than the parasitic capacitance can be reduced. And because of that the speed increases and power decreases.
The smallest layout results that the power is dissipated in the smaller area, so the self-heating effect can increase tmeperature, so, the power losses will also increase.
I think that noise is mainly caused by trasistors ans theirs parasitics. For example, when you use multi-finger transistors, the drain/sources areas are shared. As the result the drain/sources area is smaller with comparison to transistors made separately. As the results noise is also reduced.