For large digital TTL design's it was common to use one decoupling cap on each IC. Then with 50 IC's it was preferred to use a thin dielectric between the +5V and Gnd for a distributed decoupling design, where the smallest reliable gap was chosen to give the largest capacitance per sq cm. But TTL had higher impedance for Voh, and lower impedance than CMOS for Vol, so conducted noise decoupling was a little more demanding than CMOS. With CMOS, the layout of high step current into capacitive loads can be important to isolate but low ESR bulk caps can do the job with a few well placed ceramic caps per small group of ICs.
So, no need to keep Vcc/Vdd layers together, unless there are special reasons, then you would use a very thin high quality pre-preg or solid laminate to avoid shorts, much thinner than standard layers. Imagine that a track width is equal to the dielectric gap is around 50 Ohms, and CMOS drivers are as low as 25 Ohms, so if you wanted to decouple the conducted noise, the dielectric gap of the pwr/gnd layers would have to be a very small fraction of the width of the IC to get under say 0.1 Ohm.