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Layer stackup for a 6 layer board

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Newbie level 4
May 1, 2015
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I always felt it was necessary to place the gnd and pwr in the middle of the stackup.
For some reason an engineer said that isn't necessary now and he wanted them placed elsewhere.

Do users still do it the old way?

Since when has that changed? The adjacent pwr-grn plane stackup is good for high frequency bypass of high speed digital designs.

Either this isn't a digital board (RF guys tend to do things differently) or the engineer needs to read something like

Well that's good to hear. I was told a long time ago doing it that way effectively created a big "capacitor".

Well that's good to hear. I was told a long time ago doing it that way effectively created a big "capacitor".

Well I would consider it more of a distributed high frequency capacitor, big would imply something with a large value of capacitance. ;-)

Point well taken.

At page 10 of the document bellow, there is a table showing the expected performance of some stacking variants:

**broken link removed**

For large digital TTL design's it was common to use one decoupling cap on each IC. Then with 50 IC's it was preferred to use a thin dielectric between the +5V and Gnd for a distributed decoupling design, where the smallest reliable gap was chosen to give the largest capacitance per sq cm. But TTL had higher impedance for Voh, and lower impedance than CMOS for Vol, so conducted noise decoupling was a little more demanding than CMOS. With CMOS, the layout of high step current into capacitive loads can be important to isolate but low ESR bulk caps can do the job with a few well placed ceramic caps per small group of ICs.

So, no need to keep Vcc/Vdd layers together, unless there are special reasons, then you would use a very thin high quality pre-preg or solid laminate to avoid shorts, much thinner than standard layers. Imagine that a track width is equal to the dielectric gap is around 50 Ohms, and CMOS drivers are as low as 25 Ohms, so if you wanted to decouple the conducted noise, the dielectric gap of the pwr/gnd layers would have to be a very small fraction of the width of the IC to get under say 0.1 Ohm.
I just printed it and am going to study it.
Thank you for your help -- it's appreciated.

Don't forget loop area, if they are next to each other you do get some capacitance, but another advantage is similar loop areas down to the planes...
Re-read that Ti data sheet, interesting as it mentions 90 degree corners, which don't actually cause any problems till you get to GHz designs.
Look at other information as well from the likes of Henry Ott, Rlaph Morrison, Howard Johnson, Eric Bogatin etc. that is an old documents now and there is a lot around regarding this and since 2006 rise times have got faster, plus there are numerous variations on a theme... you may need to split the power layers to provide return layers for signals or to provide some capacitive screening between signal layers. The choices are endless and will be design dependant, though centre placement is a well tested basic.

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