I have tried building clock tree in icc2.but tool is not able to achieve target latency and skew, also I have one 1 Drc(trans) violation so DRC could not be the reason. From where I should start my debug for this behaviour of tool.
I have tried building clock tree in icc2.but tool is not able to achieve target latency and skew, also I have one 1 Drc(trans) violation so DRC could not be the reason. From where I should start my debug for this behaviour of tool.
Thanks for your reply!
I have just entered into project....that was set based into previous projects ( I am new in the company)....but that I know for sure that values which they have set are correct.
Could you please guide me how to debug if consider target values set is correct.
Thanks for your reply!
I have just entered into project....that was set based into previous projects ( I am new in the company)....but that I know for sure that values which they have set are correct.
Could you please guide me how to debug if consider target values set is correct.
It's hard to think that clock skew/latency can be reused from previous project unless they are very similar in size, same node, same relative number of clock tree leafs.
You may want to play with floorplanning if that is a possibility. You may want to play with the list of allowed cells for CTS. Your options are limited.
I have noticed one thing, when I used certain buffers then click latency and skew is better and comparable to target. But when I don't use those buffers it's not at all comparable.
How I can trace what difference those buffers are creating ?
One more thing I would like to add, how to decide target clock latency and skew value?
It's a tradeoff. the more you push, the faster the circuit runs, but more power it burns. you have to reason with the design spec (maybe you are obliged to hit that sweet 2GHz frequency) and with your engineering gut instinct (maybe I can save 1% here if I allow timing to degrade a bit...).