NMOS and PMOS are your explicit, desired devices. Each
has parasitic BJT "baggage". Thie baggage forms numerous
SCR structures throughout the chip and each one needs
to have a wide enough base and a stiff enough base-
emitter shunt, that SCR triggering won't happen and
holding will quench.
NMOS forms lateral NPNs to NWell and other NMOS. PMOS
in NWell is a substrate PNP, and the PMOS also have lateral
BJTs within Nwell. Any two N features in psubstrate make
lateral NPN - FET or diode, no different.
There are many good latchup tutorials and presentations.
If you aren't finding them on Google, you aren't googling
very hard. One good cross section cartoon ought to show
the mechanisms and key features in a useful way. Try
"CMOS latchup" and look at the pictures.